Enhancement of Device Performance in LDMOSFET by Using Dual-Work-Function-Gate Technique

In this letter, we propose a new lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with dual-work-function-gate (DWG) structure fabricated by utilizing silicidation of poly-Si layer. The step-etched poly-Si layer in the source side of the gate was totally converted...

Full description

Saved in:
Bibliographic Details
Published inIEEE electron device letters Vol. 31; no. 8; pp. 848 - 850
Main Authors Ha, Jong-Bong, Kang, Hee-Sung, Baek, Ki-Ju, Lee, Jung-Hee
Format Journal Article
LanguageEnglish
Published New York IEEE 01.08.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Online AccessGet full text

Cover

Loading…
Abstract In this letter, we propose a new lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with dual-work-function-gate (DWG) structure fabricated by utilizing silicidation of poly-Si layer. The step-etched poly-Si layer in the source side of the gate was totally converted to Ni-rich silicide, which resulted in a higher work function. On the other hand, in the drain side, only the upper part of the nonetched poly-Si layer was silicided, and the remaining lower part of the poly-Si layer was considered to be a gate with a lower work function. The fabricated DWG-LDMOSFET demonstrated remarkable improvement in device performances, such as 16.7, 16.4, 3.3, and 6.4% improvement in saturation drain current, in field-effect mobility, in subthreshold slope, and in the on resistance, respectively, while keeping almost the same breakdown voltage of 26 V and exhibiting less self-heating effect compared with the conventional single-work-function-gate LDMOSFET.
AbstractList In this letter, we propose a new lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with dual-work-function-gate (DWG) structure fabricated by utilizing silicidation of poly-Si layer. The step-etched poly-Si layer in the source side of the gate was totally converted to Ni-rich silicide, which resulted in a higher work function. On the other hand, in the drain side, only the upper part of the nonetched poly-Si layer was silicided, and the remaining lower part of the poly-Si layer was considered to be a gate with a lower work function. The fabricated DWG-LDMOSFET demonstrated remarkable improvement in device performances, such as 16.7, 16.4, 3.3, and 6.4% improvement in saturation drain current, in field-effect mobility, in subthreshold slope, and in the on resistance, respectively, while keeping almost the same breakdown voltage of 26 V and exhibiting less self-heating effect compared with the conventional single-work-function-gate LDMOSFET.
Author Ki-Ju Baek
Hee-Sung Kang
Jong-Bong Ha
Jung-Hee Lee
Author_xml – sequence: 1
  givenname: Jong-Bong
  surname: Ha
  fullname: Ha, Jong-Bong
– sequence: 2
  givenname: Hee-Sung
  surname: Kang
  fullname: Kang, Hee-Sung
– sequence: 3
  givenname: Ki-Ju
  surname: Baek
  fullname: Baek, Ki-Ju
– sequence: 4
  givenname: Jung-Hee
  surname: Lee
  fullname: Lee, Jung-Hee
BookMark eNpdkM1LAzEQxYMo2FbvgpeAFy9bk83H7h6lXwqVCrbobcmmE7u1TWqyK_S_N6XFg6dhmN97M_O66Nw6CwjdUNKnlBQP09Gwn5LYpURQyvgZ6lAh8oQIyc5Rh2ScJowSeYm6IawJoZxnvIM-RnalrIYt2AY7g4fwU2vAr-CN89vDBNcWT4cvs7fxaI6rPV6E2n7iYas2ybvzX8m4tbqpnU0mqgE8B72y9XcLV-jCqE2A61PtoUU0GDwl09nkefA4TTRLeZMYw6HSwhRmyUxOC6WWoqp0Kg1oVoACwYlghnHJhFYgqZSVZCAZjz9qpVkP3R99d97FtaEpt3XQsNkoC64NJZUZTZnIRR7Ru3_o2rXexutKStIsy2QuWaTIkdLeheDBlDtfb5XfR6g8RF3GqMtD1OUp6ii5PUpqAPjDBS_yXAr2C76beq0
CODEN EDLEDZ
CitedBy_id crossref_primary_10_1109_ACCESS_2020_3034572
crossref_primary_10_4313_JKEM_2012_25_9_671
crossref_primary_10_1007_s00339_020_3453_4
crossref_primary_10_1016_j_sse_2014_07_004
crossref_primary_10_1109_TED_2012_2219865
crossref_primary_10_1109_TED_2013_2278974
crossref_primary_10_1049_el_2013_1301
Cites_doi 10.1109/16.85161
10.1109/16.936703
10.1109/APEC.2009.4802896
10.1109/TED.2008.2011723
10.1109/LED.2005.861404
10.1016/j.cap.2009.04.011
10.1143/JJAP.45.1525
ContentType Journal Article
Copyright Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2010
Copyright_xml – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2010
DBID 97E
RIA
RIE
AAYXX
CITATION
7SP
8FD
L7M
F28
FR3
DOI 10.1109/LED.2010.2051134
DatabaseName IEEE All-Society Periodicals Package (ASPP) 2005-present
IEEE All-Society Periodicals Package (ASPP) 1998–Present
IEEE/IET Electronic Library (IEL)
CrossRef
Electronics & Communications Abstracts
Technology Research Database
Advanced Technologies Database with Aerospace
ANTE: Abstracts in New Technology & Engineering
Engineering Research Database
DatabaseTitle CrossRef
Technology Research Database
Advanced Technologies Database with Aerospace
Electronics & Communications Abstracts
Engineering Research Database
ANTE: Abstracts in New Technology & Engineering
DatabaseTitleList Engineering Research Database

Technology Research Database
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISSN 1558-0563
EndPage 850
ExternalDocumentID 2720438071
10_1109_LED_2010_2051134
5498865
Genre orig-research
GroupedDBID -~X
.DC
0R~
29I
4.4
5GY
5VS
6IK
97E
AAJGR
AASAJ
ABQJQ
ABVLG
ACGFO
ACIWK
ACNCT
AENEX
AETIX
AFFNX
AI.
AIBXA
AKJIK
ALLEH
ALMA_UNASSIGNED_HOLDINGS
ATWAV
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CS3
DU5
EBS
EJD
HZ~
IBMZZ
ICLAB
IFIPE
IFJZH
IPLJI
JAVBF
LAI
M43
O9-
OCL
P2P
RIA
RIE
RIG
RNS
TAE
TN5
TWZ
VH1
XFK
AAYXX
CITATION
7SP
8FD
L7M
F28
FR3
ID FETCH-LOGICAL-c324t-ff4ebc5f9fd3f819aad5bbc26fec39eae54053f34635cae6166b63e634134cac3
IEDL.DBID RIE
ISSN 0741-3106
IngestDate Fri Aug 16 23:31:00 EDT 2024
Fri Sep 13 00:51:58 EDT 2024
Fri Aug 23 01:29:44 EDT 2024
Wed Jun 26 19:20:02 EDT 2024
IsPeerReviewed true
IsScholarly true
Issue 8
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-c324t-ff4ebc5f9fd3f819aad5bbc26fec39eae54053f34635cae6166b63e634134cac3
Notes ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
PQID 1027776863
PQPubID 85488
PageCount 3
ParticipantIDs ieee_primary_5498865
proquest_miscellaneous_1671235858
proquest_journals_1027776863
crossref_primary_10_1109_LED_2010_2051134
PublicationCentury 2000
PublicationDate 2010-Aug.
2010-08-00
20100801
PublicationDateYYYYMMDD 2010-08-01
PublicationDate_xml – month: 08
  year: 2010
  text: 2010-Aug.
PublicationDecade 2010
PublicationPlace New York
PublicationPlace_xml – name: New York
PublicationTitle IEEE electron device letters
PublicationTitleAbbrev LED
PublicationYear 2010
Publisher IEEE
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml – name: IEEE
– name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
References ref7
ref9
ref4
ref3
ref5
ref2
(ref6) 0
ref1
schroder (ref8) 2006
References_xml – ident: ref1
  doi: 10.1109/16.85161
– ident: ref2
  doi: 10.1109/16.936703
– year: 2006
  ident: ref8
  publication-title: Semiconductor Material and Device Characterization
  contributor:
    fullname: schroder
– ident: ref9
  doi: 10.1109/APEC.2009.4802896
– year: 0
  ident: ref6
  publication-title: ATLAS 2-D Device Simulator
– ident: ref3
  doi: 10.1109/TED.2008.2011723
– ident: ref7
  doi: 10.1109/LED.2005.861404
– ident: ref4
  doi: 10.1016/j.cap.2009.04.011
– ident: ref5
  doi: 10.1143/JJAP.45.1525
SSID ssj0014474
Score 2.052018
Snippet In this letter, we propose a new lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with dual-work-function-gate (DWG)...
SourceID proquest
crossref
ieee
SourceType Aggregation Database
Publisher
StartPage 848
SubjectTerms Automotive engineering
Devices
Double-gate FETs
Drains
Driver circuits
Dual-work-function gate (DWG)
Electric potential
Flat panel displays
Gates
Intermetallics
lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET)
mobility
MOSFETs
Nickel
nickel silicide
Performance enhancement
Power dissipation
self-heating
Silicidation
Silicides
Voltage
Work functions
Title Enhancement of Device Performance in LDMOSFET by Using Dual-Work-Function-Gate Technique
URI https://ieeexplore.ieee.org/document/5498865
https://www.proquest.com/docview/1027776863/abstract/
https://search.proquest.com/docview/1671235858
Volume 31
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3NT9swFH8CTtthwNi08iUj7TJpLk4cO80R0VYI0W3SQOotsp1nbRpKETQH-Ovxc9KMMQ7cIsW2LL-vn9-XAT7LANJR545jlRieOZK5AgUXqBKvNRY2OnNm3_TZVXY-V_M1-NrXwiBiTD7DIX3GWH61cA25yo7DXWY00mod1kcibWu1-ohBlrUdl4OFDHpF9CFJURxfTMZtDlcaODCR2T8mKL6p8p8ijtZlugmz1b7apJI_w2Zph-7hWcvG1258C951MJOdtHyxDWtYv4e3T5oP7sB8Uv8iktNUtvBsjKQ02I-_lQTsd80uxrPvP6eTS2bvWUwvYOPGXHPysfNpsIlEV04uOHa56gb7Aa7ChNMz3r2zwF2AU0vufYbWKV_4SvqAEIyplLUu1R6dLNAgoTrpZRbAiTOoE62tlqjJAGbOOPkRNupFjZ-ACaW8scppagNDIUOTJpWocuVVVZlCDODL6ujLm7adRhmvIaIoA5lKIlPZkWkAO3SS_bjuEAewv6JV2cnbXVgjzfNwc9JyAEf97yApFP4wNS6aMEbnsTBYjXZfXnkP3rS5AZTetw8by9sGDwLkWNrDyGuPl13SOQ
link.rule.ids 315,786,790,802,27957,27958,55109
linkProvider IEEE
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3Nb9MwFH8a2wE4wGBMFPZhJC5IuHPq2GmOiLbqoB1IdFJvke08C7QpRdAc2F8_PycNjO2wW6TYluX39fP7MsBbGUA66sxxLBPDU0cyl6PgAlXitcbcRmfO_ExPz9NPS7XcgvddLQwixuQz7NNnjOWXK1eTq-wk3GWGQ60ewE6w8yJvqrW6mEGaNj2Xg40MmkV0QUmRn8zGoyaLaxB4MJHpDSMUX1W5pYqjfZk8hflmZ01ayUW_Xtu-u_qvaeN9t74LT1qgyT40nPEMtrB6Do__aT-4B8tx9Z2ITlPZyrMRktpgX__WErAfFZuN5l--TcYLZv-wmGDARrW55ORl55NgFYmynJxwbLHpB_sCzsOEj1PevrTAXQBUa-59itYpn_tS-oARjCmVtW6gPTqZo0HCddLLNMATZ1AnWlstUZMJTJ1xch-2q1WFL4EJpbyxymlqBENBQzNISlFmyquyNLnowbvN0Rc_m4YaRbyIiLwIZCqITEVLph7s0Ul249pD7MHBhlZFK3G_wxqDLAt3Jy178Kb7HWSFAiCmwlUdxugslgar4au7Vz6Gh9PFfFbMTs8-v4ZHTaYAJfsdwPb6V42HAYCs7VHku2vaY9WP
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Enhancement+of+Device+Performance+in+LDMOSFET+by+Using+Dual-Work-Function-Gate+Technique&rft.jtitle=IEEE+electron+device+letters&rft.au=Jong-Bong+Ha&rft.au=Hee-Sung+Kang&rft.au=Ki-Ju+Baek&rft.au=Jung-Hee+Lee&rft.date=2010-08-01&rft.issn=0741-3106&rft.eissn=1558-0563&rft.volume=31&rft.issue=8&rft.spage=848&rft.epage=850&rft_id=info:doi/10.1109%2FLED.2010.2051134&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_LED_2010_2051134
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0741-3106&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0741-3106&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0741-3106&client=summon