Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL

• Published in: IEEE transactions on power electronics Vol. 26; no. 4; pp. 1067 - 1080
• Main Authors: Wang, Yi Fei, Wei Li, Yun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Conditioning; Control systems; Delay; Delayed signal cancellation (DSC); Differential scanning calorimetry; Digital; Digital electronics; discretization error; Electric potential; Electric power; Electrical equipment; Errors; grid synchronization; Harmonic analysis; Harmonics; Operators; Phase locked loops; phase-locked loop (PLL); Power system harmonics; Time domain analysis; Time frequency analysis; Voltage; Voltage control

Phase-locked loop (PLL) is usually required to detect grid phase angle in grid-tied converters. Conventional PLL schemes have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To overcome this challenge, a generalized delayed...