An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip

The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between th...

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Published inWireless personal communications Vol. 128; no. 4; pp. 2937 - 2952
Main Authors Kumar, Aruru Sai, Naresh Kumar Reddy, B.
Format Journal Article
LanguageEnglish
Published New York Springer US 01.02.2023
Springer Nature B.V
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Abstract The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between them improves in order to solve such problems. Throughput and latency both have a higher impact on outperforming the network’s performance in NoC. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM is presented. In this algorithm, based on the minimum core average distance the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research is evaluated on a set of embedded applications, which reveals a reduction in latency at 12.3% and 8.4%, the simulation time reduces at an average of 19% and 9.6%, the throughput increases at 14.5% and 7.8% and reduces the communication energy by 15.6% and 5.2% against Branch and Bound Based Mapping (BBPCR) and segmented brute-force mapping respectively. The proposed ERTEAM is simulated and tested on Xilinxs Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2020.2 software platform. The obtained hardware implementation results outperformed the delay and area metrics.
AbstractList The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between them improves in order to solve such problems. Throughput and latency both have a higher impact on outperforming the network’s performance in NoC. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM is presented. In this algorithm, based on the minimum core average distance the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research is evaluated on a set of embedded applications, which reveals a reduction in latency at 12.3% and 8.4%, the simulation time reduces at an average of 19% and 9.6%, the throughput increases at 14.5% and 7.8% and reduces the communication energy by 15.6% and 5.2% against Branch and Bound Based Mapping (BBPCR) and segmented brute-force mapping respectively. The proposed ERTEAM is simulated and tested on Xilinxs Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2020.2 software platform. The obtained hardware implementation results outperformed the delay and area metrics.
Author Naresh Kumar Reddy, B.
Kumar, Aruru Sai
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Issue 4
Keywords Core mapping
Real-time embedded applications
Performance
System on Chip (SoC)
Network on Chip (NoC)
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  doi: 10.1109/ACCESS.2021.3066537
– ident: 10080_CR18
  doi: 10.1007/s11235-017-0412-2
– volume: 16
  start-page: 1
  year: 2017
  ident: 10080_CR15
  publication-title: Sustainable Computing: Informatics and Systems
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Snippet The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the...
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SubjectTerms Algorithms
Communication
Communications Engineering
Computer Communication Networks
Engineering
Mapping
Multiprocessing
Network latency
Networks
Performance measurement
Real time
Signal,Image and Speech Processing
System on chip
Title An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip
URI https://link.springer.com/article/10.1007/s11277-022-10080-x
https://www.proquest.com/docview/2779449680
Volume 128
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