An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip
The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between th...
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Published in | Wireless personal communications Vol. 128; no. 4; pp. 2937 - 2952 |
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Main Authors | , |
Format | Journal Article |
Language | English |
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Springer US
01.02.2023
Springer Nature B.V |
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Abstract | The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between them improves in order to solve such problems. Throughput and latency both have a higher impact on outperforming the network’s performance in NoC. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM is presented. In this algorithm, based on the minimum core average distance the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research is evaluated on a set of embedded applications, which reveals a reduction in latency at 12.3% and 8.4%, the simulation time reduces at an average of 19% and 9.6%, the throughput increases at 14.5% and 7.8% and reduces the communication energy by 15.6% and 5.2% against Branch and Bound Based Mapping (BBPCR) and segmented brute-force mapping respectively. The proposed ERTEAM is simulated and tested on Xilinxs Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2020.2 software platform. The obtained hardware implementation results outperformed the delay and area metrics. |
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AbstractList | The Network on Chip architecture’s performance metrics and inter-core communication are significantly impacted by the acceleration of the evolution of the components integrated on a single chip. Therefore, it is crucial to offer an effective mapping between the cores so that communication between them improves in order to solve such problems. Throughput and latency both have a higher impact on outperforming the network’s performance in NoC. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM is presented. In this algorithm, based on the minimum core average distance the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research is evaluated on a set of embedded applications, which reveals a reduction in latency at 12.3% and 8.4%, the simulation time reduces at an average of 19% and 9.6%, the throughput increases at 14.5% and 7.8% and reduces the communication energy by 15.6% and 5.2% against Branch and Bound Based Mapping (BBPCR) and segmented brute-force mapping respectively. The proposed ERTEAM is simulated and tested on Xilinxs Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit using Xilinx Vivado 2020.2 software platform. The obtained hardware implementation results outperformed the delay and area metrics. |
Author | Naresh Kumar Reddy, B. Kumar, Aruru Sai |
Author_xml | – sequence: 1 givenname: Aruru Sai orcidid: 0000-0001-7924-8575 surname: Kumar fullname: Kumar, Aruru Sai email: asaikumar.nitw@gmail.com organization: Department of ECE, VNR Vignana Jyothi Institute of Engineering and Technology – sequence: 2 givenname: B. surname: Naresh Kumar Reddy fullname: Naresh Kumar Reddy, B. organization: Department of Electronics and Communication Engineering, National Institute of Technology |
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Keywords | Core mapping Real-time embedded applications Performance System on Chip (SoC) Network on Chip (NoC) |
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References | Wu (CR21) 2015; 34 Beechu, Harishchandra, Balachandra (CR15) 2017; 16 CR18 CR17 CR13 CR10 Reddy, Vasantha, Nithin Kumar (CR24) 2018; 68 Becchu (CR19) 2017; 70 Kumar, Rao, Reddy (CR20) 2022; 41 Li, Wu, Ma (CR6) 2007; 12 Khan, Anjum, Gulzari, Umer, Kim (CR12) 2018; 6 CR3 Beechu, Moodabettu Harishchandra, Yernad Balachandra (CR14) 2018; 100 Li, Wang, Singh, Mak (CR5) 2019; 30 CR25 Jiang, Li, Wang, Wei (CR8) 2015; 7 CR23 Jagadheesh (CR2) 2022; 10 CR22 Kumar, Hanumantha Rao (CR4) 2020; 79 Bhanu, Govindan, Kattamuri, Soumya, Cenkeramaddi (CR9) 2021; 9 Liu (CR11) 2015; 23 Liu (CR7) 2018; 67 Beechu, Harishchandra, Balachandra (CR16) 2017; 105 Benini, Micheli (CR1) 2002; 35 W Liu (10080_CR7) 2018; 67 G Jiang (10080_CR8) 2015; 7 AS Kumar (10080_CR20) 2022; 41 L Liu (10080_CR11) 2015; 23 PV Bhanu (10080_CR9) 2021; 9 10080_CR17 10080_CR3 10080_CR18 S Khan (10080_CR12) 2018; 6 G Li (10080_CR6) 2007; 12 10080_CR13 S Jagadheesh (10080_CR2) 2022; 10 NKR Beechu (10080_CR15) 2017; 16 10080_CR10 C Wu (10080_CR21) 2015; 34 L Benini (10080_CR1) 2002; 35 B Li (10080_CR5) 2019; 30 B Reddy (10080_CR24) 2018; 68 AS Kumar (10080_CR4) 2020; 79 NKR Beechu (10080_CR16) 2017; 105 N Beechu (10080_CR14) 2018; 100 10080_CR25 NKR Becchu (10080_CR19) 2017; 70 10080_CR23 10080_CR22 |
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SubjectTerms | Algorithms Communication Communications Engineering Computer Communication Networks Engineering Mapping Multiprocessing Network latency Networks Performance measurement Real time Signal,Image and Speech Processing System on chip |
Title | An Efficient Real-Time Embedded Application Mapping for NoC Based Multiprocessor System on Chip |
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