Hardware Architecture Exploration for Deep Neural Networks

• Published in: Arabian journal for science and engineering (2011) Vol. 46; no. 10; pp. 9703 - 9712
• Main Authors: Zheng, Wenqi, Zhao, Yangyi, Chen, Yunfan, Park, Jinhong, Shin, Hyunchul
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.10.2021; Springer Nature B.V
• Subjects: Artificial intelligence; Artificial neural networks; Chips (memory devices); Computation; Computer architecture; Design; Design optimization; Dynamic random access memory; Engineering; Hardware; Humanities and Social Sciences; Machine learning; Modules; multidisciplinary; Neural networks; Power consumption; Research Article-Electrical Engineering; Science; Specifications; Static random access memory; CNN; AI architecture; Neural network architecture; Design space exploration

Owing to good performance, deep Convolution Neural Networks (CNNs) are rapidly rising in popularity across a broad range of applications. Since high accuracy CNNs are both computation intensive and memory intensive, many researchers have shown significant interest in the accelerator design. Furtherm...