Hardware Architecture Exploration for Deep Neural Networks

• Published in: Arabian journal for science and engineering (2011) Vol. 46; no. 10; pp. 9703 - 9712
• Main Authors: Zheng, Wenqi, Zhao, Yangyi, Chen, Yunfan, Park, Jinhong, Shin, Hyunchul
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.10.2021; Springer Nature B.V
• Subjects: Artificial intelligence; Artificial neural networks; Chips (memory devices); Computation; Computer architecture; Design; Design optimization; Dynamic random access memory; Engineering; Hardware; Humanities and Social Sciences; Machine learning; Modules; multidisciplinary; Neural networks; Power consumption; Research Article-Electrical Engineering; Science; Specifications; Static random access memory; CNN; AI architecture; Neural network architecture; Design space exploration
• DOI: 10.1007/s13369-021-05455-4
• ISSN: 2193-567X; 1319-8025

Owing to good performance, deep Convolution Neural Networks (CNNs) are rapidly rising in popularity across a broad range of applications. Since high accuracy CNNs are both computation intensive and memory intensive, many researchers have shown significant interest in the accelerator design. Furthermore, the AI chip market size grows and the competition on the performance, cost, and power consumption of the artificial intelligence SoC designs is increasing. Therefore, it is important to develop design techniques and platforms that are useful for the efficient design of optimized AI architectures to satisfy the given specifications in a short design time. In this research, we have developed design space exploration techniques and environments for the optimal design of the overall system including computing modules and memories. Our current design platform is built using NVIDIA Deep Learning Accelerator as a computing model, SRAM as a buffer, and DRAM with GDDR6 as an off-chip memory. We also developed a program to estimate the processing time of a given neural network. By modifying both the on-chip SRAM size and the computing module size, a designer can explore the design space efficiently, and then choose the optimal architecture which shows the minimal cost while satisfying the performance specification. To illustrate the operation of the design platform, two well-known deep CNNs are used, which are YOLOv3 and faster RCNN. This technology can be used to explore and to optimize the hardware architectures of the CNNs so that the cost can be minimized.