Process evaluation in FinFET based 7T SRAM cell

• Published in: Analog integrated circuits and signal processing Vol. 109; no. 3; pp. 545 - 551
• Main Authors: Kumar, T. Santosh, Tripathi, Suman Lata
• Format: Journal Article
• Language: English
• Published: New York Springer US 01.12.2021; Springer Nature B.V
• Subjects: Circuits and Systems; Electric potential; Electrical Engineering; Engineering; Leakage; Low temperature; Power management; Retention; Signal,Image and Speech Processing; Stability; Static random access memory; Topology; Transistors; Voltage; Process variations; Low power; SRAM cell etc; Process corners; Data retention voltage; FinFET
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-021-01938-4

The main aim of device scaling or usage of different technology is to reduce power. The major problem with technology scaling is power dissipation and stability of the device. SRAM is an integral part of any memory, different topologies are proposed in SRAM to address the problem of power dissipation and stability in nanometer technologies. FinFET based devices have proven to be the better alternative for having low power dissipation in any SRAM. In the low dimension devices, the process variations have to be considered in low power applications. In this paper data retention voltage, a parameter used for estimation of cell stability is considered and also the leakage power with a variation of transistor functionality. Cadence Virtuoso tool is used to evaluate process corner analysis with 18 nm FinFET technology. The data retention voltage in fast-slow (FS) corner is low and it is high in fast–fast (FF) corner at low temperatures and when the temperature is high FF corner has a high data retention voltage. Similarly, the leakage power is low at the TT process corner maintaining stability.