Effective Wire Models for X-Architecture Placement

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 4; pp. 654 - 658
• Main Authors: Chen, Tung-Chieh, Chuang, Yi-Lin, Chang, Yao-Wen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Circuit optimization; Computer aided design; Costs; Delay; Design engineering; Geometry; Integrated circuit interconnections; Mathematical analysis; Mathematical models; Min-cut; net weighting; Partitioning; Partitioning algorithms; physical design; Pins; Placement; Routing; Steiner tree; Wire; Wiring; X architecture
• DOI: 10.1109/TCAD.2008.917959
• ISSN: 0278-0070

In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the XHPWL model, and the X-Steiner wirelength (XStWL) model. For min-cut partitioning placement, we apply the XHPWL and XStWL models to the generalized net-weighting method that can exactly model the wirelength after partitioning by net weighting. For analytical placement, we smooth the XHPWL function using log-sum-exp functions to facilitate analytical placement. This paper shows that both the XHPWL and XStWL models can reduce the X wirelength effectively. In particular, our results reveal the effectiveness of the X architecture on wirelength reduction during placement and, thus, the importance of the study on the X-placement algorithms, which is different from the results given in the work of Ono et al. which suggests that the X-architecture placement might not improve the X-routing wirelength over the Manhattan-architecture placement.