Effects of source/drain elevation and side spacer dielectric on drivability performance of non-abrupt ultra shallow junction gate underlap GAA MOSFETs

• Published in: Indian journal of physics Vol. 92; no. 2; pp. 171 - 176
• Main Authors: Singh, Kunal, Kumar, Sanjay, Goel, Ekta, Singh, Balraj, Singh, Prince Kumar, Baral, Kamalaksha, Kumar, Hemant, Jit, Satyabrata
• Format: Journal Article
• Language: English
• Published: New Delhi Springer India 01.02.2018; Springer Nature B.V
• Subjects: Astrophysics and Astroparticles; Dielectrics; Elevation; Hafnium oxide; MOSFETs; Original Paper; Physics; Physics and Astronomy; Silicon dioxide; 85.30.Kk; Gate all around (GAA); 85.30.Tv; Elevated source/drain (E-S/D); Gate underlap; On/Off current ratio; Ultra shallow junction (USJ); 85.30.-z
• ISSN: 0973-1458; 0974-9845
• DOI: 10.1007/s12648-017-1091-2

Present work focuses on quantitative effects of source/drain elevation height ( h SD ) and side spacer dielectric material (Air, SiO 2 , Si 3 N 4 and HfO 2 ) on the current drive of non-abrupt ultra shallow junction (USJ) gate all around (GAA) MOSFETs. It has been observed that the desirable unanimous reverse trend (increase in I on and decrease in I off with increase in source/drain elevation height ( h SD ) and/or side spacer dielectric constant, ε sp ). Utmost percentage improvement in I on / I off ratio at h SD = 30.5 nm and σ L = 7 nm is found to be ~3000% for HfO 2 while least as ~449% for Air with respect to their corresponding values at zero elevation. Thus, the increase in source/drain elevation with proper selection of side spacer is found to be a suitable approach. This will enhance the drivability as well as lower parasitic resistance in comparison to non elevated GAA MOSFETs at sub 20 nm technology node.