A Highly Linear Low-Voltage Source-Degeneration Transconductor Based on Unity-Gain Buffer

A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor...

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Published inTsinghua science and technology Vol. 14; no. 6; pp. 698 - 702
Main Author 孔耀晖 刘爱荣 杨华中
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.12.2009
Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
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ISSN1007-0214
1878-7606
1007-0214
DOI10.1016/S1007-0214(09)70137-3

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Abstract A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion (THD) for a 1-MHz 0.4-Vp-p differential input signal. The third-order intermodulation is less than -63 dB for 0.25 Vp-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.
AbstractList A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage.Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion (THD) for a 1-MHz 0.4-Vp-p differential input signal.The third-order intermodulation is less than-63 dB for 0.25 Vp-p differential inputs at 1 MHz.The DC power consumption in the transconductor core is 240 μW.This topology is a feasible solution for low voltage and low power applications.
A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion (THD) for a 1-MHz 0.4-Vp-p differential input signal. The third-order intermodulation is less than -63 dB for 0.25 Vp-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.
A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-μm standard CMOS process with a 1.2-V supply voltage has less than −80 dB total harmonic distortion (THD) for a 1-MHz 0.4-V p-p differential input signal. The third-order intermodulation is less than −63 dB for 0.25 V p-p differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 μW. This topology is a feasible solution for low voltage and low power applications.
A complementary metal oxide semiconductor (CMOS) transconductor based on a high performance unity-gain buffer driving the degeneration resistor was used to obtain a highly linear voltage-to-current conversion with considerable reduction of the supply voltage. Simulations show that the transconductor using an 0.18-km standard CMOS process with a 1.2-V supply voltage has less than -80 dB total harmonic distortion (THD) for a 1-MHz 0.4-V(p-p) differential input signal. The third-order intermodulation is less than -63 dB for 0.25 V(p-p) differential inputs at 1 MHz. The DC power consumption in the transconductor core is 240 kW. This topology is a feasible solution for low voltage and low power applications.
Author 孔耀晖 刘爱荣 杨华中
AuthorAffiliation Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
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SubjectTerms CMOS工艺
high linearity
low power
low voltage
transconductor
unity gain buffer
互补金属氧化物半导体
单位增益
电压源
电源电压
缓冲器
高线性
Title A Highly Linear Low-Voltage Source-Degeneration Transconductor Based on Unity-Gain Buffer
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