Reliable sizing of power networks in VLSI circuits

• Published in: Computer aided design Vol. 24; no. 6; pp. 291 - 300
• Main Authors: Chowdhury, S., Barkatullah, J.S.
• Format: Journal Article
• Language: English
• Published: Oxford Elsevier Ltd 01.06.1992; Elsevier Science
• Subjects: Applied sciences; Computer aided design; Computer science; control theory; systems; Exact sciences and technology; graph topology; power networks; sizing; Software; sizing; graph topology; power networks; Fault tolerance; VLSI circuit; Electrical network; Optimal solution; Integrated circuit; Routing; Power supply; Topology; Computer aided design

The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant desig...