Reliable sizing of power networks in VLSI circuits
The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant desig...
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| Published in | Computer aided design Vol. 24; no. 6; pp. 291 - 300 |
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| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
Oxford
Elsevier Ltd
01.06.1992
Elsevier Science |
| Subjects | |
| Online Access | Get full text |
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| Abstract | The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant design or redundancy at the higher levels. The widths of the power/ground nets are determined subject to the assumed constraints. An attempt is made to reduce the metal area required. Experimental results for examples and runtimes are included. |
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| AbstractList | The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant design or redundancy at the higher levels. The widths of the power/ground nets are determined subject to the assumed constraints. An attempt is made to reduce the metal area required. Experimental results for examples and runtimes are included. |
| Author | Chowdhury, S. Barkatullah, J.S. |
| Author_xml | – sequence: 1 givenname: S. surname: Chowdhury fullname: Chowdhury, S. – sequence: 2 givenname: J.S. surname: Barkatullah fullname: Barkatullah, J.S. |
| BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=5569529$$DView record in Pascal Francis |
| BookMark | eNp9kEtLAzEURoMoWKv_wMUsRHQxepNJppONIK2PQkHwtQ1p5kai06QmU4v-eqe2dOnqbs534J4DsuuDR0KOKVxQoOUlAIWc80qcSXYuAXiZj3ZIj1YDmbOyErukt0X2yUFK7wDAaCF7hD1i4_S0wSy5H-ffsmCzeVhizDy2yxA_UuZ89jp5GmfGRbNwbToke1Y3CY82t09ebm-eh_f55OFuPLye5Kagos1ZTbXESgoj0HBLKwH1YDoFQZkVpRWiYpaWRTEAXtemAzUaBMO5ZSCptUWfnK698xg-F5haNXPJYNNoj2GRFBOdUpSsA082oE5GNzZqb1xS8-hmOn4rIUopmOwwvsZMDClFtFuCglp1VKtIahVJSab-OqpRN7taz7D79cthVMk49AZrF9G0qg7uf8Evmal5_w |
| CODEN | CAIDA5 |
| Cites_doi | 10.1109/JSSC.1986.1052491 10.1109/43.3949 10.1109/TCS.1987.1086084 |
| ContentType | Journal Article |
| Copyright | 1992 1992 INIST-CNRS |
| Copyright_xml | – notice: 1992 – notice: 1992 INIST-CNRS |
| DBID | AAYXX CITATION IQODW 8FD F28 FR3 |
| DOI | 10.1016/0010-4485(92)90046-D |
| DatabaseName | CrossRef Pascal-Francis Technology Research Database ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
| DatabaseTitle | CrossRef Technology Research Database ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Applied Sciences |
| EISSN | 1879-2685 |
| EndPage | 300 |
| ExternalDocumentID | 5569529 10_1016_0010_4485_92_90046_D 001044859290046D |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 1B1 1~. 1~5 29F 4.4 457 4G. 5GY 5VS 6TJ 7-5 71M 8P~ 9JN AABNK AACTN AAEDT AAEDW AAIAV AAIKC AAIKJ AAKOC AALRI AAMNW AAOAW AAQFI AAQXK AAXUO AAYFN ABAOU ABBOA ABEFU ABFNM ABFRF ABMAC ABXDB ABYKQ ACAZW ACBEA ACDAQ ACGFO ACGFS ACIWK ACKIV ACNNM ACRLP ACZNC ADBBV ADEZE ADGUI ADJOM ADMUD ADTZH AEBSH AECPX AEFWE AEKER AENEX AFFNX AFKWA AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIGVJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD ARUGR ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q G8K GBLVA GBOLZ HLZ HVGLF HZ~ IHE J1W JJJVA K-O KOM LG9 LY7 M41 MHUIS MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. PQQKQ Q38 R2- RIG RNS ROL RPZ RXW SBC SDF SDG SDP SES SET SEW SPC SPCBC SST SSV SSW SSZ T5K TAE TN5 TWZ VOH WUQ XFK XPP ZMT ~G- AATTM AAXKI AAYWO AAYXX ABDPE ABJNI ABWVN ACRPL ACVFH ADCNI ADNMO AEIPS AEUPX AFJKZ AFPUW AFXIZ AGCQF AGQPQ AGRNS AIGII AIIUN AKBMS AKRWK AKYEP ANKPU APXCP BNPGV CITATION SSH EFKBS IQODW 8FD F28 FR3 |
| ID | FETCH-LOGICAL-c315t-2d1a9e895c5ec4f1850d7bb0512f56f5582f1633704ddce89aece0c44f2091ff3 |
| ISSN | 0010-4485 |
| IngestDate | Fri Jul 11 02:57:34 EDT 2025 Mon Jul 21 09:12:00 EDT 2025 Tue Jul 01 03:34:18 EDT 2025 Fri Feb 23 02:29:14 EST 2024 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 6 |
| Keywords | sizing graph topology power networks Fault tolerance VLSI circuit Electrical network Optimal solution Integrated circuit Routing Power supply Topology Computer aided design |
| Language | English |
| License | https://www.elsevier.com/tdm/userlicense/1.0 CC BY 4.0 |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c315t-2d1a9e895c5ec4f1850d7bb0512f56f5582f1633704ddce89aece0c44f2091ff3 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| PQID | 25850562 |
| PQPubID | 23500 |
| PageCount | 10 |
| ParticipantIDs | proquest_miscellaneous_25850562 pascalfrancis_primary_5569529 crossref_primary_10_1016_0010_4485_92_90046_D elsevier_sciencedirect_doi_10_1016_0010_4485_92_90046_D |
| ProviderPackageCode | CITATION AAYXX |
| PublicationCentury | 1900 |
| PublicationDate | 1992-06-01 |
| PublicationDateYYYYMMDD | 1992-06-01 |
| PublicationDate_xml | – month: 06 year: 1992 text: 1992-06-01 day: 01 |
| PublicationDecade | 1990 |
| PublicationPlace | Oxford |
| PublicationPlace_xml | – name: Oxford |
| PublicationTitle | Computer aided design |
| PublicationYear | 1992 |
| Publisher | Elsevier Ltd Elsevier Science |
| Publisher_xml | – name: Elsevier Ltd – name: Elsevier Science |
| References | Branin (BIB1) 1980 Black (BIB7) 1969; Vol 57 Fiacco, McCormick (BIB8) 1968 Chowdhury, Breuer (BIB5) 1987 Chowdhury, Breuer (BIB3) Jun 1988 Song, Glasser (BIB2) Feb 1986 Mead, Conway (BIB6) 1980 Choma (BIB4) 1985 Chowdhury (10.1016/0010-4485(92)90046-D_BIB3) 1988 Choma (10.1016/0010-4485(92)90046-D_BIB4) 1985 Mead (10.1016/0010-4485(92)90046-D_BIB6) 1980 Branin (10.1016/0010-4485(92)90046-D_BIB1) 1980 Song (10.1016/0010-4485(92)90046-D_BIB2) 1986 Black (10.1016/0010-4485(92)90046-D_BIB7) 1969; Vol 57 Chowdhury (10.1016/0010-4485(92)90046-D_BIB5) 1987 Fiacco (10.1016/0010-4485(92)90046-D_BIB8) 1968 |
| References_xml | – start-page: 787 year: Jun 1988 end-page: 796 ident: BIB3 article-title: Optimum design of IC power/ground nets subject to reliability constraints publication-title: IEEE Trans. Comput.-Aided Des. – start-page: 785 year: 1980 end-page: 790 ident: BIB1 article-title: The analysis and design of power distribution nets on LSI chips publication-title: Proc. Int. Conf. Circuits & Computers – year: 1985 ident: BIB4 article-title: Electrical Networks — Theory and Analysis – year: 1968 ident: BIB8 article-title: Nonlinear Programming: Sequential Unconstrained Minimization Techniques – volume: Vol 57 start-page: 1587 year: 1969 end-page: 1594 ident: BIB7 article-title: Electromigration failure modes in aluminium metallization for semiconductor devices publication-title: Proc. IEEE – year: Feb 1986 ident: BIB2 article-title: Power distribution techniques for VLSI circuits publication-title: J. Solid State Circuits – start-page: 1441 year: 1987 end-page: 1451 ident: BIB5 article-title: Minimal area design of power/ground nets having graph topologies publication-title: IEEE Trans. Circuits & Syst. – year: 1980 ident: BIB6 article-title: Introduction to VLSI Systems – year: 1986 ident: 10.1016/0010-4485(92)90046-D_BIB2 article-title: Power distribution techniques for VLSI circuits publication-title: J. Solid State Circuits doi: 10.1109/JSSC.1986.1052491 – year: 1968 ident: 10.1016/0010-4485(92)90046-D_BIB8 – start-page: 787 year: 1988 ident: 10.1016/0010-4485(92)90046-D_BIB3 article-title: Optimum design of IC power/ground nets subject to reliability constraints publication-title: IEEE Trans. Comput.-Aided Des. doi: 10.1109/43.3949 – volume: Vol 57 start-page: 1587 year: 1969 ident: 10.1016/0010-4485(92)90046-D_BIB7 article-title: Electromigration failure modes in aluminium metallization for semiconductor devices – start-page: 1441 year: 1987 ident: 10.1016/0010-4485(92)90046-D_BIB5 article-title: Minimal area design of power/ground nets having graph topologies publication-title: IEEE Trans. Circuits & Syst. doi: 10.1109/TCS.1987.1086084 – year: 1980 ident: 10.1016/0010-4485(92)90046-D_BIB6 – year: 1985 ident: 10.1016/0010-4485(92)90046-D_BIB4 – start-page: 785 year: 1980 ident: 10.1016/0010-4485(92)90046-D_BIB1 article-title: The analysis and design of power distribution nets on LSI chips |
| SSID | ssj0002139 |
| Score | 1.3898717 |
| Snippet | The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered.... |
| SourceID | proquest pascalfrancis crossref elsevier |
| SourceType | Aggregation Database Index Database Publisher |
| StartPage | 291 |
| SubjectTerms | Applied sciences Computer aided design Computer science; control theory; systems Exact sciences and technology graph topology power networks sizing Software |
| Title | Reliable sizing of power networks in VLSI circuits |
| URI | https://dx.doi.org/10.1016/0010-4485(92)90046-D https://www.proquest.com/docview/25850562 |
| Volume | 24 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV3da9RAEF_0-qKIWD_w1LZ5UFCOnMlmNx-PpVeprfhgW-3bsp_0EHLlLofQv97Zr8SjitqXEDabLMxMZn6zOx8IvZbWzKgcPFVhdEp0RlNAGWWqai24FkIZ4aItPpdH5-T4gl4MTRBddkknpvL6t3klt-EqjAFfbZbsf3C2_ygMwD3wF67AYbj-E49tPLFLfVrNr2P0su16Nml9cLeLdf366fTjRM6Xcj33VZv6wgShocPEVolUE7URy3FwufihLsMh--l02PBcfucduK3cbcccT8MjFRLp8BDf5DezYkLLED3kFCSoZfDY_EGz9jqxrpoUl2EsKE2f-ByEY0MD-uZbwZgWrgzpTT3ttwz61QBMN_iNtYzgrqezwTb1EYOujhDMBDRn58zuoi0MjgEeoa39ky_fTnrri_PCuzzh0zFdMi_f92NvG_wuLPUnOPLgiq_gJzG-u8kNQ-3Qx9kj9DC4Dcm-l4FtdEe3j9H9X4pJPkE4SkPipSFZmMRJQxKlIZm3iZWGJErDU3T-4fDs4CgNHTFSWeS0S7HKeaPrhkqqJTGAtTJVCQGKFRtaGkprbABgF1VGlJIwkWupM0mIwYALjSmeoVG7aPVzlJSkMjlVsiRlQWojeJPzymZdkwIbTbIxSiNh2JUvfMJiRKAlJLOEZA1mjpBsNkZVpB4L4M2DMgY8_8ubOxvE7pejtGwobsZoLxKfge6zB1q81Yv1imHwdS2Af3HrtV-ie8O_8QqNuuVa7wDK7MRuEKyfogp0ig |
| linkProvider | Library Specific Holdings |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Reliable+sizing+of+power+networks+in+VLSI+circuits&rft.jtitle=Computer+aided+design&rft.au=Chowdhury%2C+S.&rft.au=Barkatullah%2C+J.S.&rft.date=1992-06-01&rft.pub=Elsevier+Ltd&rft.issn=0010-4485&rft.eissn=1879-2685&rft.volume=24&rft.issue=6&rft.spage=291&rft.epage=300&rft_id=info:doi/10.1016%2F0010-4485%2892%2990046-D&rft.externalDocID=001044859290046D |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0010-4485&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0010-4485&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0010-4485&client=summon |