Reliable sizing of power networks in VLSI circuits

The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant desig...

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Bibliographic Details
Published inComputer aided design Vol. 24; no. 6; pp. 291 - 300
Main Authors Chowdhury, S., Barkatullah, J.S.
Format Journal Article
LanguageEnglish
Published Oxford Elsevier Ltd 01.06.1992
Elsevier Science
Subjects
Applied sciences
Computer aided design
Computer science; control theory; systems
Exact sciences and technology
graph topology
power networks
sizing
Software
sizing
graph topology
power networks
Fault tolerance
VLSI circuit
Electrical network
Optimal solution
Integrated circuit
Routing
Power supply
Topology
Computer aided design
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Summary:The paper deals with sizing power/ground nets in integrated circuits. Certain reliability constraints such as voltage drop and metal migration are considered. These reliability constraints exist at the lowest level of physical design, and cannot be overcome by techniques such as fault-tolerant design or redundancy at the higher levels. The widths of the power/ground nets are determined subject to the assumed constraints. An attempt is made to reduce the metal area required. Experimental results for examples and runtimes are included.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0010-4485
1879-2685
DOI:10.1016/0010-4485(92)90046-D