Newly developed process integration technologies for highly reliable 40 nm ReRAM

• Published in: Japanese Journal of Applied Physics Vol. 58; no. SB; p. SBBB06
• Main Authors: Yoneda, Shinichi, Ito, Satoru, Hayakawa, Yukio, Wei, Zhiqiang, Muraoka, Shunsaku, Yasuhara, Ryutaro, Kawashima, Koichi, Himeno, Atsushi, Mikawa, Takumi
• Format: Journal Article
• Language: English
• Published: IOP Publishing 01.04.2019
• ISSN: 0021-4922; 1347-4065
• DOI: 10.7567/1347-4065/aafd8d

We have developed a 40 nm resistive random access memory (ReRAM) technology embedded in a foundry-standard CMOS process for low-power applications. Excellent reliability was achieved in 8 Mbit, 40 nm ReRAM: 100 k cycles and 10 year retention at 85 °C after 10 k cycles were demonstrated for resistive switching element (RSE) process technologies and filament characterization methods. Regarding process technologies for 40 nm ReRAM, we tackled four forms of integration. First, we experimented with RSE etching, to optimize damage-less etching of RSE, metal and dielectric. Second, we tried to maintain the back end of line process/parameter compatibility with the standard 40 nm CMOS process. Third, we developed our own techniques to form RSE cells that are protected against extra free oxygen to realize design flexibility. Fourth, we optimized the components of the high-resistivity layer (Ta2O5), specifically film density, and confirmed that it is possible to achieve both ease of occurrence of formation and reduced non-uniformity of the resistance values corresponding to the high resistive state.