A 2-D semi-analytical model of double-gate tunnel field-effect transistor

A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunctio...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductors Vol. 36; no. 5; pp. 24 - 30
Main Author 许会芳 代月花 李宁 徐建斌
Format Journal Article
LanguageEnglish
Published 01.05.2015
Subjects
Electric potential
Field effect transistors
Gates (circuits)
Mathematical models
Semiconductors
Thickness
Tunneling
Voltage
二维泊松方程
半解析方法
半解析模型
场效应晶体管
栅极
电势分布
级数表达式
隧道长度
Online AccessGet full text
ISSN1674-4926
DOI10.1088/1674-4926/36/5/054002

Cover

Abstract A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
AbstractList A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
A 2-D semi-analytical model of double gate (DG) tunneling field-effect transistor (TFET) is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane's model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
Author 许会芳 代月花 李宁 徐建斌
AuthorAffiliation Institute of Electronic and Information Engineering, Anhui University, Hefei 230601, China
Author_xml – sequence: 1
  fullname: 许会芳 代月花 李宁 徐建斌
BookMark eNqFkD9PwzAQxT0UibbwEZAiJhZTOz47iZiq8q9SJRaYLSexi5Fjt7Ez9NuTqlUHFqbTPb3fO92boYkPXiN0R8kjJWW5oKIADFUuFkws-IJwICSfoOlFv0azGH8IGXegU7ReZjl-zqLuLFZeuUOyjXJZF1rtsmCyNgy103irks7S4P2oGqtdi7UxuklZ6pWPNqbQ36Aro1zUt-c5R1-vL5-rd7z5eFuvlhvcMMoSVozyitVFpdqKawBVUyNUXhECuSqFEK0uCeVtU9SCQV3QmtYchCIMWmNIxebo4ZS768N-0DHJzsZGO6e8DkOUtByjBKcAo5WfrE0fYuy1kbvedqo_SErksS55rEUea5FMSC5PdY3c0x-usUklG_z4rnX_0vdn-jv47d767eWsECAKBlCxX0UZfg0
CitedBy_id crossref_primary_10_1016_j_spmi_2021_107063
crossref_primary_10_2174_2210681207666170612081017
Cites_doi 10.1063/1.3658871
10.1016/j.sse.2011.06.012
10.1063/1.3168646
10.1109/TED.2012.2209180
10.1109/TED.2008.916711
10.1109/TED.2014.2329372
10.1063/1.3277044
10.1109/TED.2010.2040661
10.1109/TED.2009.2028055
10.1016/0022-3697(60)90035-4
10.1063/1.3567021
10.1016/j.sse.2011.05.008
10.1109/TED.2010.2089525
10.1063/1.3466908
10.1109/TED.2014.2313037
10.1109/TED.2012.2191556
10.1063/1.1699487
ContentType Journal Article
DBID 2RA
92L
CQIGP
W92
~WA
AAYXX
CITATION
7SP
7U5
8FD
L7M
DOI 10.1088/1674-4926/36/5/054002
DatabaseName 维普_期刊
中文科技期刊数据库-CALIS站点
中文科技期刊数据库-7.0平台
中文科技期刊数据库-工程技术
中文科技期刊数据库- 镜像站点
CrossRef
Electronics & Communications Abstracts
Solid State and Superconductivity Abstracts
Technology Research Database
Advanced Technologies Database with Aerospace
DatabaseTitle CrossRef
Solid State and Superconductivity Abstracts
Technology Research Database
Advanced Technologies Database with Aerospace
Electronics & Communications Abstracts
DatabaseTitleList
Solid State and Superconductivity Abstracts
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
Physics
DocumentTitleAlternate A 2-D semi-analytical model of double-gate tunnel field-effect transistor
EndPage 30
ExternalDocumentID 10_1088_1674_4926_36_5_054002
664673449
GroupedDBID 02O
042
1WK
2B.
2C0
2RA
4.4
5B3
5VR
5VS
7.M
92H
92I
92L
92R
93N
AAGCD
AAJIO
AALHV
AATNI
ABHWH
ACAFW
ACGFO
ACGFS
ACHIP
AEFHF
AFUIB
AFYNE
AHSEE
AKPSB
ALMA_UNASSIGNED_HOLDINGS
ASPBG
AVWKF
AZFZN
BBWZM
CCEZO
CEBXE
CHBEP
CJUJL
CQIGP
CRLBU
CUBFJ
CW9
EBS
EDWGO
EJD
EQZZN
FA0
IJHAN
IOP
IZVLO
JCGBZ
KNG
KOT
M45
N5L
NS0
NT-
NT.
PJBAE
Q02
RIN
RNS
ROL
RPA
RW3
SY9
TCJ
TGT
W28
W92
~WA
-SI
-S~
5XA
5XJ
AAYXX
ACARI
AERVB
AGQPQ
AOAED
ARNYC
CAJEI
CITATION
Q--
TGMPQ
U1G
U5S
7SP
7U5
8FD
L7M
ID FETCH-LOGICAL-c313t-a31593b79ad95e44ab1f6a290042a8666de8015dc7b634b71b1b546a034dff093
ISSN 1674-4926
IngestDate Fri Jul 11 00:02:00 EDT 2025
Tue Jul 01 03:20:30 EDT 2025
Thu Apr 24 23:12:48 EDT 2025
Wed Feb 14 10:31:05 EST 2024
IsPeerReviewed true
IsScholarly true
Issue 5
Language English
License http://iopscience.iop.org/info/page/text-and-data-mining
http://iopscience.iop.org/page/copyright
LinkModel OpenURL
MergedId FETCHMERGED-LOGICAL-c313t-a31593b79ad95e44ab1f6a290042a8666de8015dc7b634b71b1b546a034dff093
Notes A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane＇s model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.
Xu Huifang, Dai Yuehua, Li Ning, and Xu Jianbin Institute of Electronic and Information Engineering, Anhui University, Hefei 230601, China
11-5781/TN
semi-analytical method; eigenfunction expansion method; double-gate tunnel field effect transistor （TFET）; surface potential; drain current
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
PQID 1800465144
PQPubID 23500
PageCount 7
ParticipantIDs proquest_miscellaneous_1800465144
crossref_primary_10_1088_1674_4926_36_5_054002
crossref_citationtrail_10_1088_1674_4926_36_5_054002
chongqing_primary_664673449
ProviderPackageCode CITATION
AAYXX
PublicationCentury 2000
PublicationDate 2015-05-01
PublicationDateYYYYMMDD 2015-05-01
PublicationDate_xml – month: 05
  year: 2015
  text: 2015-05-01
  day: 01
PublicationDecade 2010
PublicationTitle Journal of semiconductors
PublicationTitleAlternate Chinese Journal of Semiconductors
PublicationYear 2015
References 11
12
13
14
Vishnoi R (19) 1936; 61
16
17
18
(15) 2009
1
2
3
4
5
6
7
9
Chen Y (8) 2006; 27
20
10
References_xml – ident: 10
  doi: 10.1063/1.3658871
– volume: 61
  issn: 0018-9383
  year: 1936
  ident: 19
  publication-title: IEEE Trans Electron Devices
– ident: 16
  doi: 10.1016/j.sse.2011.06.012
– ident: 4
  doi: 10.1063/1.3168646
– year: 2009
  ident: 15
  publication-title: ALTAS Device Simulation Software
– ident: 17
  doi: 10.1109/TED.2012.2209180
– ident: 2
  doi: 10.1109/TED.2008.916711
– ident: 20
  doi: 10.1109/TED.2014.2329372
– ident: 9
  doi: 10.1063/1.3277044
– ident: 1
  doi: 10.1109/TED.2010.2040661
– ident: 5
  doi: 10.1109/TED.2009.2028055
– ident: 14
  doi: 10.1016/0022-3697(60)90035-4
– ident: 7
  doi: 10.1063/1.3567021
– ident: 13
  doi: 10.1016/j.sse.2011.05.008
– ident: 3
  doi: 10.1109/TED.2010.2089525
– ident: 6
  doi: 10.1063/1.3466908
– ident: 11
  doi: 10.1109/TED.2014.2313037
– ident: 12
  doi: 10.1109/TED.2012.2191556
– ident: 18
  doi: 10.1063/1.1699487
– volume: 27
  start-page: 852
  issn: 0899-9988
  year: 2006
  ident: 8
  publication-title: Chinese Journal of Semiconductors
SSID ssj0067441
Score 1.9911485
Snippet A 2-D semi-analytical model of double gate （DG） tunneling field-effect transistor （TFET） is proposed. By aid of introducing two rectangular sources located in...
A 2-D semi-analytical model of double gate (DG) tunneling field-effect transistor (TFET) is proposed. By aid of introducing two rectangular sources located in...
SourceID proquest
crossref
chongqing
SourceType Aggregation Database
Enrichment Source
Index Database
Publisher
StartPage 24
SubjectTerms Electric potential
Field effect transistors
Gates (circuits)
Mathematical models
Semiconductors
Thickness
Tunneling
Voltage
二维泊松方程
半解析方法
半解析模型
场效应晶体管
栅极
电势分布
级数表达式
隧道长度
Title A 2-D semi-analytical model of double-gate tunnel field-effect transistor
URI http://lib.cqvip.com/qk/94689X/201505/664673449.html
https://www.proquest.com/docview/1800465144
Volume 36
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV1Lb9QwELagCAkOCAqIpYCCxG3lbhI_4hxXPNRWvA6ttJws27HblUpCu8mFX8_YeW6pgHKJoiieSJ4vM-Px-BuE3ghOiGWOYWVEjmlmCqwzRzApOFWZc5mJ_UHhT5_5wQk9WrHVWKcbTpfUet_8vPZcyf9oFZ6BXv0p2RtodhAKD-Ae9AtX0DBc_0nHy3mK38039vsaK08u0ualQ3MbHwQWVaPPbcigzevGF7TMQ8Eabos4fHuIctPzDV8XonrJsF72lLDVuOuzaoK_atZOdW4vZLpDWcC3xp41g6X_uG7BNr7Wjj0CTOqO8rvLOCRsrO_rjCTPKPZEg1Mr2tKYdGhhE5MIIWE4U_27sQYD5_MGvTS4D-1lAtnFMGqbIvuK6xoKCsNWuhDSC5NemCRcMtmKuY3upLCI8P0tDr987f00vBn6mg7f7893CbEYni0IX7BFK8azb5xV5ekFzNp2FLPtxENkcvwQPej0FS1bfDxCt2y5i-5PiCZ30d1Q6Gs2j9HhMgLMRFcwEwXMRJWLJpiJWsxEU8xEI2aeoJMP74_fHuCunQY2JCE1VgRCV6KzXBU5s5QqnTiu0tzbbSVgGVtYCFdYYTLNCdVZohPNKFcxoYVzcU6eop2yKu0zFKUOfuE4KVwWG2pcKhS1QjsB3iqJi9TO0N4wVfJHS5siOQenTCjNZ4j2kydNx0TvG6Kcyz-qcYb2h2G9zL8MeN1rRoLR9DthqrRVs5GJ8HkhWCvQ5zcVuofujf_EC7RTXzb2JcSltX4V4PULUoeCzQ
linkProvider IOP Publishing
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+2-D+semi-analytical+model+of+double-gate+tunnel+field-effect+transistor&rft.jtitle=Journal+of+semiconductors&rft.au=Xu%2C+Huifang&rft.au=Dai%2C+Yuehua&rft.au=Li%2C+Ning&rft.au=Xu%2C+Jianbin&rft.date=2015-05-01&rft.issn=1674-4926&rft.volume=36&rft.issue=5&rft.spage=54002&rft_id=info:doi/10.1088%2F1674-4926%2F36%2F5%2F054002&rft.externalDBID=n%2Fa&rft.externalDocID=10_1088_1674_4926_36_5_054002
thumbnail_s http://utb.summon.serialssolutions.com/2.0.0/image/custom?url=http%3A%2F%2Fimage.cqvip.com%2Fvip1000%2Fqk%2F94689X%2F94689X.jpg