An ultra-low-power area-efficient non-volatile memory in a 0.18μm single-poly CMOS process for passive RFID tags
This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling duri...
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Published in | Journal of semiconductors Vol. 34; no. 8; pp. 94 - 98 |
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Format | Journal Article |
Language | English |
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01.08.2013
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Abstract | This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s). |
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AbstractList | This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 mu m single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 mu m single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 mu m super(2) and 0.12 mm super(2), respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V. The power consumption of the read/write operation is 0.19 mu W/0.69 mu W at a read/write rate of (268 kb/s)/(3.0 kb/s). This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s). |
Author | 贾晓云 冯鹏 张胜广 吴南健 赵柏秦 刘肃 |
AuthorAffiliation | State Key Laboratory for Super Lattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences,Beijing 100083, China Institute of Microelectronics, School of Physical Science and Technology, Lanzhou University, Lanzhou 730000, China |
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Cites_doi | 10.1002/9780470665121 10.1088/1674-4926/32/5/055009 10.1109/4.278354 10.1088/1674-4926/32/11/115013 |
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DocumentTitleAlternate | An ultra-low-power area-efficient non-volatile memory in a 0.18μm single-poly CMOS process for passive RFID tags |
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Notes | 11-5781/TN This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s). non-volatile memory ultra-low-power area-efficient CMOS RFID ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
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PublicationTitle | Journal of semiconductors |
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References | Pan L (7) 2008 Zhao D (9) 2008; 29 Pikhay E (10) 2012 5 Wang Yaowen (3) 2011; 32 Raszka J (6) 2004; 1 Finkenzeller K (1) 2010 Yin J (4) 2010; 45 Feng P (8) 2009 Feng Peng (2) 2011; 32 |
References_xml | – year: 2010 ident: 1 publication-title: RFID handbook: fundamentals and applications in contactless smart cards, radio frequency identification and near-field communication identification doi: 10.1002/9780470665121 contributor: fullname: Finkenzeller K – start-page: 1827 year: 2012 ident: 10 contributor: fullname: Pikhay E – volume: 45 start-page: 2404 issn: 0018-9200 year: 2010 ident: 4 publication-title: IEEE J. Solid-State Circuits contributor: fullname: Yin J – volume: 29 start-page: 1 year: 2008 ident: 9 publication-title: J. Semiconductors contributor: fullname: Zhao D – volume: 1 start-page: 46 year: 2004 ident: 6 publication-title: IEEE ISSCC Dig Tech Papers contributor: fullname: Raszka J – volume: 32 start-page: 055009 year: 2011 ident: 3 publication-title: J. Semiconductors doi: 10.1088/1674-4926/32/5/055009 contributor: fullname: Wang Yaowen – ident: 5 doi: 10.1109/4.278354 – start-page: 197 year: 2008 ident: 7 contributor: fullname: Pan L – start-page: 713 year: 2009 ident: 8 contributor: fullname: Feng P – volume: 32 start-page: 115013 issn: 1674-4926 year: 2011 ident: 2 publication-title: J. Semiconductors doi: 10.1088/1674-4926/32/11/115013 contributor: fullname: Feng Peng |
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Snippet | This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency... This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 mu m single-poly standard CMOS process for passive radio frequency... |
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SubjectTerms | Arrays CMOS CMOS工艺 Memory (computers) Radio frequency identification RFID标签 Semiconductors Tags Voltage 多晶硅 无源 记忆体 超低功耗 非挥发性 面积 |
Title | An ultra-low-power area-efficient non-volatile memory in a 0.18μm single-poly CMOS process for passive RFID tags |
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