An ultra-low-power area-efficient non-volatile memory in a 0.18μm single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling duri...

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Bibliographic Details
Published inJournal of semiconductors Vol. 34; no. 8; pp. 94 - 98
Main Author 贾晓云 冯鹏 张胜广 吴南健 赵柏秦 刘肃
Format Journal Article
LanguageEnglish
Published 01.08.2013
Subjects
Arrays
CMOS
CMOS工艺
Memory (computers)
Radio frequency identification
RFID标签
Semiconductors
Tags
Voltage
多晶硅
无源
记忆体
超低功耗
非挥发性
面积
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Summary:This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.
Bibliography:11-5781/TN
This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.
non-volatile memory ultra-low-power area-efficient CMOS RFID
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ISSN:1674-4926
DOI:10.1088/1674-4926/34/8/085004