Robust RTL power macromodels

In this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units. Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 6; no. 4; pp. 578 - 581
Main Authors Bogliolo, A., Benini, L.
Format Journal Article
LanguageEnglish
Published IEEE 01.12.1998
Subjects
Circuit simulation
Circuit synthesis
Digital circuits
Energy consumption
Logic
Power dissipation
Robustness
Sampling methods
Software libraries
Statistics
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Summary:In this paper, we propose a robust register-transfer level (RTL) power modeling methodology for functional units. Our models are consistently accurate over a wide range of input statistics, they are automatically constructed and can provide pattern-by-pattern power estimates. An additional desirable feature of our modeling methodology is the capability of accounting for the impact of technology variations, library changes and synthesis tools. Our methodology is based on the concept of node sampling, as opposed to more traditional approaches based on input sampling.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1063-8210
1557-9999
DOI:10.1109/92.736131