Software-hardware co-design for accelerating large-scale graph convolutional network inference on FPGA

• Published in: Neurocomputing (Amsterdam) Vol. 532; pp. 129 - 140
• Main Authors: Ran, Shaolin, Zhao, Beizhen, Dai, Xing, Cheng, Cheng, Zhang, Yong
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.05.2023
• Subjects: FPGA; Graph convolutional network; Graph sparsification; Hardware acceleration; Software-hardware co-design; Software-hardware co-design; Graph convolutional network; Graph sparsification; FPGA; Hardware acceleration

Inspired by convolutional neural networks, graph convolutional networks (GCNs) have been proposed for processing non-Euclidean graph data and successfully been applied in recommendation systems, smart traffic, etc. However, subject to the sparsity and irregularity of GCN models, the complex executio...