APA (7th ed.) Citation

Ran, S., Zhao, B., Dai, X., Cheng, C., & Zhang, Y. (2023). Software-hardware co-design for accelerating large-scale graph convolutional network inference on FPGA. Neurocomputing (Amsterdam), 532, 129-140. https://doi.org/10.1016/j.neucom.2023.02.032

Chicago Style (17th ed.) Citation

Ran, Shaolin, Beizhen Zhao, Xing Dai, Cheng Cheng, and Yong Zhang. "Software-hardware Co-design for Accelerating Large-scale Graph Convolutional Network Inference on FPGA." Neurocomputing (Amsterdam) 532 (2023): 129-140. https://doi.org/10.1016/j.neucom.2023.02.032.

MLA (9th ed.) Citation

Ran, Shaolin, et al. "Software-hardware Co-design for Accelerating Large-scale Graph Convolutional Network Inference on FPGA." Neurocomputing (Amsterdam), vol. 532, 2023, pp. 129-140, https://doi.org/10.1016/j.neucom.2023.02.032.