Highly testable design of BiCMOS logic circuits

• Published in: IEEE journal of solid-state circuits Vol. 29; no. 6; pp. 671 - 678
• Main Authors: Osman, M.Y., Elmasry, M.I.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.06.1994; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; BiCMOS integrated circuits; Circuit faults; Circuit testing; Design for testability; Electronics; Exact sciences and technology; Fault detection; Integrated circuits; Logic circuits; Logic design; Logic gates; Logic testing; Propagation delay; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Logic circuit; Current sensor; Test; Complementary MOS technology; Integrated circuit; Theoretical study; Self control; Numerical simulation; Bipolar technology; Computer aided design
• DOI: 10.1109/4.293112
• ISSN: 0018-9200

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%.< >