Recent advances in VLSI layout
The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and...
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| Published in | Proceedings of the IEEE Vol. 78; no. 2; pp. 237 - 263 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
New York, NY
IEEE
01.02.1990
Institute of Electrical and Electronics Engineers |
| Subjects | |
| Online Access | Get full text |
| ISSN | 0018-9219 |
| DOI | 10.1109/5.52212 |
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| Abstract | The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and building-block designs are examined. The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size. Global routing based on a method of successive cuts on a chip is discussed. This is a hierarchical top-down approach that is useful for both of the above designs. A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed. The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.< > |
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| AbstractList | Because of advances made in automatic placement and routing, application specific integrated circuit (ASIC) design now represents a sizeable portion of the chip market. The influence of computer-aided physical design will continue to be felt in the future; for example, in further popularizing the sea-of-gates and building-block design styles. Recent advances in floor planning and placement and in global and detailed routing pertinent to these design styles are reviewed. Also included are the subjects of computational geometry and layout engines. The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and building-block designs are examined. The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size. Global routing based on a method of successive cuts on a chip is discussed. This is a hierarchical top-down approach that is useful for both of the above designs. A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed. The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.< > |
| Author | Kuh, E.S. Ohtsuki, T. |
| Author_xml | – sequence: 1 givenname: E.S. surname: Kuh fullname: Kuh, E.S. organization: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA – sequence: 2 givenname: T. surname: Ohtsuki fullname: Ohtsuki, T. |
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| Keywords | Technical progress VLSI circuit Integrated circuit Application specific circuit Routing Layout problem Review Computer aided design |
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| Snippet | The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and... Because of advances made in automatic placement and routing, application specific integrated circuit (ASIC) design now represents a sizeable portion of the... |
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| StartPage | 237 |
| SubjectTerms | Application software Application specific integrated circuits Applied sciences Computational geometry Design automation Design. Technologies. Operation analysis. Testing Electronics Engines Exact sciences and technology Grid computing Integrated circuits Physics computing Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Simulated annealing Very large scale integration |
| Title | Recent advances in VLSI layout |
| URI | https://ieeexplore.ieee.org/document/52212 https://www.proquest.com/docview/25861279 |
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