Recent advances in VLSI layout

• Published in: Proceedings of the IEEE Vol. 78; no. 2; pp. 237 - 263
• Main Authors: Kuh, E.S., Ohtsuki, T.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.1990; Institute of Electrical and Electronics Engineers
• Subjects: Application software; Application specific integrated circuits; Applied sciences; Computational geometry; Design automation; Design. Technologies. Operation analysis. Testing; Electronics; Engines; Exact sciences and technology; Grid computing; Integrated circuits; Physics computing; Routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulated annealing; Very large scale integration; Technical progress; VLSI circuit; Integrated circuit; Application specific circuit; Routing; Layout problem; Review; Computer aided design
• ISSN: 0018-9219
• DOI: 10.1109/5.52212

The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and building-block designs are examined. The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size. Global routing based on a method of successive cuts on a chip is discussed. This is a hierarchical top-down approach that is useful for both of the above designs. A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed. The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered.< >