Novel Frequency Hopping Sequences Generator Based on AES Algorithm
A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security.A high...
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| Published in | Transactions of Tianjin University Vol. 16; no. 1; pp. 22 - 27 |
|---|---|
| Main Author | |
| Format | Journal Article |
| Language | English |
| Published |
Heidelberg
Tianjin University
01.02.2010
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics, Xidian University, Xi'an 710071, China |
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| Online Access | Get full text |
| ISSN | 1006-4982 1995-8196 |
| DOI | 10.1007/s12209-010-0005-6 |
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| Abstract | A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security.A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying ... |
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| AbstractList | O4; A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES)iterated block cipher is proposed for FH communication systems. The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security. A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying the dynamic clock gating technology based on finite state machine and clock gating. SMIC 0.18 μm standard CMOS technology shows that the scale of ASIC is only about 10.68 kgate, power consumption is 33.8 μW/MHz, and the maximum hop-rate is 1 098 901 hop/s. This design is suitable for portable FH communication system for its advantages in high-security and hop-rate, low-power and low-cost. The proposed FH sequences generator has been employed in Bluetooth SoC design. A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES) iterated block cipher is proposed for FH communication systems. The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security. A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying the dynamic clock gating technology based on finite state machine and clock gating. SMIC 0.18km standard CMOS technology shows that the scale of ASIC is only about 10.68 kgate, power consumption is 33.8kW/MHz, and the maximum hop-rate is 1 098 901 hop/s. This design is suitable for portable FH communication system for its advantages in high-security and hop-rate, low-power and low-cost. The proposed FH sequences generator has been employed in Bluetooth SoC design. A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES) iterated block cipher is proposed for FH communication systems. The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security. A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying the dynamic clock gating technology based on finite state machine and clock gating. SMIC 0.18 μm standard CMOS technology shows that the scale of ASIC is only about 10.68 kgate, power consumption is 33.8 μW/MHz, and the maximum hop-rate is 1 098 901 hop/s. This design is suitable for portable FH communication system for its advantages in high-security and hop-rate, low-power and low-cost. The proposed FH sequences generator has been employed in Bluetooth SoC design. A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security.A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying ... |
| Author | 李振荣 庄奕琪 张博 张超 |
| AuthorAffiliation | Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of Microelectronics Xidian University |
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| Keywords | low-cost low-power application specific integrated circuit advanced encryption standard frequency hopping sequences |
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| Snippet | A novel frequency hopping(FH) sequences generator based on advanced encryption standard(AES) iterated block cipher is proposed for FH communication systems.The... A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES) iterated block cipher is proposed for FH communication systems.... O4; A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES)iterated block cipher is proposed for FH communication... |
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| Title | Novel Frequency Hopping Sequences Generator Based on AES Algorithm |
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