APA (7th ed.) Citation

Tripathy, M. R., Singh, A. K., Baral, K., Singh, P. K., & Jit, S. (2020). III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications. Superlattices and microstructures, 142, 106494. https://doi.org/10.1016/j.spmi.2020.106494

Chicago Style (17th ed.) Citation

Tripathy, Manas Ranjan, Ashish Kumar Singh, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit. "III-V/Si Staggered Heterojunction Based Source-pocket Engineered Vertical TFETs for Low Power Applications." Superlattices and Microstructures 142 (2020): 106494. https://doi.org/10.1016/j.spmi.2020.106494.

MLA (9th ed.) Citation

Tripathy, Manas Ranjan, et al. "III-V/Si Staggered Heterojunction Based Source-pocket Engineered Vertical TFETs for Low Power Applications." Superlattices and Microstructures, vol. 142, 2020, p. 106494, https://doi.org/10.1016/j.spmi.2020.106494.