Numerical analysis of Mg2Si/Si heterojunction DG-TFET for low power/high performance applications: Impact of non- idealities

• Published in: Superlattices and microstructures Vol. 139; p. 106397
• Main Authors: Madan, Jaya, Dassi, Minaxi, Pandey, Rahul, Chaujar, Rishu, Sharma, Rajnish
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.03.2020
• Subjects: Band to band tunneling; Bulk defects; DG-TFET; Magnesium silicide; Staggered type heterojunction; Tunnel FET; DG-TFET; Staggered type heterojunction; Tunnel FET; Magnesium silicide; Band to band tunneling; Bulk defects
• ISSN: 0749-6036; 1096-3677
• DOI: 10.1016/j.spmi.2020.106397

In the advanced technology nodes, conventional MOSFETs are being replaced by tunnel field effect transistors (TFETs), due to its potential of achieving subthreshold swing (SS) less than 60 mV/decade. However, certain constraints are to be met to improve the performance of TFET in terms of higher ON current (ION) and lower threshold voltage (Vth). Here, in this paper, magnesium silicide/silicon (Mg2Si/Si) heterojunction double gate TFET (Mg2Si/Si HDG-TFET) is explored and is simultaneously compared with conventional silicon double gate TFET (Si DG-TFET). Results depict superior performance of Mg2Si/Si HDG-TFET as compared to conventional Si DG-TFET, in terms of dc characteristics, i.e., ION, Vth, SS, and ION/IOFF ratio. Obtained Vth (0.26 V), SS (10.05mV/decade) and ION/IOFF ratio (1013) for the case of Mg2Si HDG-TFET shows an improvement of 77%, 49% and 10 decades respectively compared to counterpart i.e., Si DG-TFET. In particular, this improvement in the performance of Mg2Si/Si HDG-TFET over Si DG-TFET is attributed to staggered type-II heterojunction interface at the source-channel junction, which leads to reduction of the width for interband tunneling barrier and hence, improves ION. This viability of the device is also determined by analyzing the impact of non-idealities present in the device. In this respect, the Gaussian and tail defects are considered in the bulk of Mg2Si. The results reveal that the Gaussian defects alter the device characteristics mainly in the subthreshold regime, whereas, in the ON state, the impact of defects is minimal. Further, it is obtained that the device is much immune for tail defects in comparison with the Gaussian defects. The CV analysis reveals a marginal degradation in parasitic capacitances for Mg2Si/Si HDG-TFET as compared to Si DG-TFET. However, this degradation can be overlooked against the remarkably enhanced drain current. Thus, the device overcomes the bottleneck of TFET and provides high ION and low Vth without degrading the other performance parameters and hence is suitable for low power analog and digital applications. •Mg2Si/Si heterojunction DG-TFET has been proposed.•Impact of presence of non-idealities such as Gaussian and tail defects is analyzed.•Staggered type-II heterojunction interface of Mg2Si/Si conquer bottleneck of TFET.•Proposed device is suitable for low power analog and digital applications.