APA (7th ed.) Citation

Aghandeh, H., & Sedigh Ziabari, S. A. (2017). Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement. Superlattices and microstructures, 111, 103-114. https://doi.org/10.1016/j.spmi.2017.06.018

Chicago Style (17th ed.) Citation

Aghandeh, Hadi, and Seyed Ali Sedigh Ziabari. "Gate Engineered Heterostructure Junctionless TFET with Gaussian Doping Profile for Ambipolar Suppression and Electrical Performance Improvement." Superlattices and Microstructures 111 (2017): 103-114. https://doi.org/10.1016/j.spmi.2017.06.018.

MLA (9th ed.) Citation

Aghandeh, Hadi, and Seyed Ali Sedigh Ziabari. "Gate Engineered Heterostructure Junctionless TFET with Gaussian Doping Profile for Ambipolar Suppression and Electrical Performance Improvement." Superlattices and Microstructures, vol. 111, 2017, pp. 103-114, https://doi.org/10.1016/j.spmi.2017.06.018.