Coherence controller architectures for scalable shared-memory multiprocessors

Scalable distributed shared-memory architectures rely on coherence controllers on each processing node to synthesize cache-coherent shared memory across the entire machine. The coherence controllers execute coherence protocol handlers that may be hardwired in custom hardware or programmed in a proto...

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Bibliographic Details
Published inIEEE transactions on computers Vol. 48; no. 2; pp. 245 - 255
Main Authors Michael, M.M., Nanda, A.K., Beng-Hong Lim
Format Journal Article
LanguageEnglish
Published IEEE 01.02.1999
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