A 70-MHz 1.2- mu m CMOS 16-point DFT processor

• Published in: IEEE journal of solid-state circuits Vol. 23; no. 2; pp. 343 - 350
• Main Authors: Linderman, R.W., Shephard, C.G., Taylor, K., Coutee, P.W., Rossbach, P.C., Collins, J.M., Hauser, R.S.
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.1988
• Subjects: Algorithm design and analysis; Arithmetic; Circuit testing; CMOS process; Computer architecture; Design for testability; Discrete Fourier transforms; Electrical fault detection; Packaging; Throughput
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.994

A chip architecture designed to compute a 16-point discrete Fourier transform (DFT) using S. Winograd's algorithm (1978) every 457 ns is presented. The 99500-transistor 1.2- mu m chip incorporates arithmetic, control, and input/output circuitry with testability and fault detection into a 144-pin package. A throughput of 2.3*10/sup 12/ gate-Hz/cm/sup 2/ and 79-million multiplications/s is attained with 70-MHz pipelined bit-serial logic. Combined with similar chips computing 15- and 17-point DFTs, 4080-point DFTs can be computed every 118 mu s. Using the 16- and 17-point chips, 272*272-point complex data imagery can be transformed in 4.25 ms. A 24-bit block floating-point data representation combined with an adaptive scaling algorithm delivers a numerical precision of 106 dB (17.6 bits) after computing 4080-point DFTs.< >