Pre-Defined Sparse Neural Networks With Hardware Acceleration

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 9; no. 2; pp. 332 - 345
• Main Authors: Dey, Sourya, Huang, Kuan-Wen, Beerel, Peter A., Chugg, Keith M.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Artificial intelligence; Artificial neural networks; Complexity; Complexity theory; Computation; Computer architecture; Energy storage; Field programmable gate arrays; Hardware; hardware acceleration; Inference; Junctions; Machine learning; multilayer perceptron; Multilayer perceptrons; neural network; Neural networks; Neurons; Sparsity; Training

Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors. This paper presents two compatible contributions towards reducing the time, energy, computational, and storage complexities as...