Pre-Defined Sparse Neural Networks With Hardware Acceleration

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 9; no. 2; pp. 332 - 345
• Main Authors: Dey, Sourya, Huang, Kuan-Wen, Beerel, Peter A., Chugg, Keith M.
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Artificial intelligence; Artificial neural networks; Complexity; Complexity theory; Computation; Computer architecture; Energy storage; Field programmable gate arrays; Hardware; hardware acceleration; Inference; Junctions; Machine learning; multilayer perceptron; Multilayer perceptrons; neural network; Neural networks; Neurons; Sparsity; Training
• DOI: 10.1109/JETCAS.2019.2910864
• ISSN: 2156-3357

Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors. This paper presents two compatible contributions towards reducing the time, energy, computational, and storage complexities associated with multilayer perceptrons. Pre-defined sparsity is proposed to reduce the complexity during both training and inference, regardless of the implementation platform. Our results show that storage and computational complexity can be reduced by factors greater than 5X without significant performance loss. The second contribution is an architecture for hardware acceleration that is compatible with pre-defined sparsity. This architecture supports both training and inference modes and is flexible in the sense that it is not tied to a specific number of neurons. For example, this flexibility implies that various sized neural networks can be supported on various sized field programmable gate array (FPGA)s.