Study of interface-trap and near-interface-state distribution in a 4H-SiC MOS capacitor with the full-distributed circuit model

• Published in: Japanese Journal of Applied Physics Vol. 63; no. 1; pp. 15503 - 15511
• Main Authors: Van Cuong, Vuong, Koyanagi, Kaho, Meguro, Tatsuya, Ishikawa, Seiji, Maeda, Tomonori, Sezaki, Hiroshi, Kuroki, Shin-Ichiro
• Format: Journal Article
• Language: English
• Published: Tokyo IOP Publishing 01.01.2024; Japanese Journal of Applied Physics
• Subjects: Capacitance; Capacitors; Circuits; Dispersion; distributed circuit; harsh environment; high temperature; interface trap; MOS; Near-interface state; silicon carbide
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/ad169b

Abstract In this research, the full-distributed circuit model was used to classify the contribution of interface traps (ITs) and near-interface states to the electrical characteristics of a 4H-SiC MOS capacitor over a wide range of operation. By fitting the measured capacitance and conductance at a certain value of applied gate voltage when the frequency varied from 1 kHz to 1 MHz, the density of both near-interface states and ITs was determined. The results reveal that, at RT, the frequency dispersion of capacitance in the depletion condition is mainly caused by the contribution of ITs. Nevertheless, in the strong accumulation condition, near-interface states become dominant for the frequency dispersion of the capacitance. Furthermore, the full-distributed circuit model also successfully explained the electrical characteristics of a 4H-SiC MOS capacitor when operating at 500 °C.