HIPU: A Hybrid Intelligent Processing Unit With Fine-Grained ISA for Real-Time Deep Neural Network Inference Applications

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 31; no. 12; pp. 1980 - 1993
• Main Authors: Zhao, Wenzhe, Yang, Guoming, Xia, Tian, Chen, Fei, Zheng, Nanning, Ren, Pengju
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Algorithms; Artificial neural networks; Convolution; Design optimization; Inference; Inference algorithms; Matrix converters; Network-on-chip (NoC); neural network (NN) inference accelerating; Neural networks; Operators; out-of-order (OoO) superscalar processor; Performance enhancement; Real time; Real-time systems; reduced instruction set architecture; Schedules; Task analysis

Neural network algorithms have shown superior performance over conventional algorithms, leading to the designation and deployment of dedicated accelerators in practical scenarios. Coarse-grained accelerators achieve high performance but can support only a limited number of predesigned operators, whi...