Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 32; no. 3; pp. 592 - 596
• Main Authors: Ahmadi, Kasra, Aghapour, Saeed, Kermani, Mehran Mozaffari, Azarderakhsh, Reza
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Clocks; Cryptography; Curves; Elliptic curve cryptography; Error correction & detection; Error correction codes; Error detection; Fault detection; Field programmable gate arrays; field-programmable gate array (FPGA); Hardware; Multiplication; reliability; Very large scale integration; window method
• DOI: 10.1109/TVLSI.2023.3341147
• ISSN: 1063-8210

Elliptic curve scalar multiplication (ECSM) stands as a crucial subblock in elliptic curve cryptography (ECC), which represents the most widely used prequantum public key cryptography. Hardware constructions of cryptographic systems utilizing ECSM have been subject to permanent or transient errors. In cryptographic systems, it is important to validate the correctness of the underlying computation performed on hardware or software to identify such errors. In this article, we present new fault detection schemes in window method scalar multiplication, which, to the best of our knowledge, has not been previously investigated. Our approach involves introducing refined algorithms and implementations that can effectively counter both permanent and transient errors. We assess this by simulating a fault model, ensuring that the evaluations conducted reflect the obtained results. As a result, we achieve a significantly extensive coverage of errors. Finally, we benchmark our proposed error detection scheme on ARMv8 and field-programmable gate array (FPGA) to demonstrate the implementation and resource overhead. On Cortex-A72 processors, we maintain a clock cycle overhead of under 3%. In addition, when implementing our error detection method on different FPGAs, including Zynq Ultrascale+, Artix-7, and Kintex Ultrascale+, we achieve comparable throughput while introducing a mere 2% increase in area compared with the original hardware implementations.