High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 8; pp. 1874 - 1885
• Main Authors: Lian, Xiaocong, Liu, Zhenyu, Song, Zhourui, Dai, Jiwu, Zhou, Wei, Ji, Xiangyang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Artificial neural networks; Block floating point (BFP); Computational modeling; Computer memory; Computer vision; convolutional neural network (CNN) accelerator; Embedded systems; Feature maps; Field programmable gate arrays; field-programmable gate array (FPGA); Floating point arithmetic; Hardware; Mathematical model; Memory management; Neural networks; Quantization (signal); Retraining; Rounding; Speech processing; three-level parallel

Convolutional neural networks (CNNs) are widely used and have achieved great success in computer vision and speech processing applications. However, deploying the large-scale CNN model in the embedded system is subject to the constraints of computation and memory. An optimized block-floating-point (...