POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 3; pp. 838 - 842
• Main Authors: Bank-Tavakoli, Erfan, Ghasemzadeh, Seyed Abolfazl, Kamal, Mehdi, Afzali-Kusha, Ali, Pedram, Massoud
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Computer architecture; Field programmable gate arrays; Field-programmable gate array (FPGA); Hardware; high speed; Logic gates; long short-term memory (LSTM) accelerator; low power; low resource utilization; Mapping; Power demand; Power efficiency; Power management; Resource management; Resource utilization; Timing

In this brief, a low resource utilization field-programmable gate array (FPGA)-based long short-term memory (LSTM) network architecture for accelerating the inference phase is presented. The architecture has low-power and high-speed features that are achieved through overlapping the timing of the op...