Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers

• Published in: IEEE transactions on communications Vol. 65; no. 3; pp. 1234 - 1246
• Main Authors: Wadhwa, Aseem, Madhow, Upamanyu, Shanbhag, Naresh R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; analog to digital converter; Analog to digital converters; Analog-digital conversion; Architecture; Bandwidths; Context; Design standards; Dispersion; Equalization; Equalizers; Error detection; fractionally spaced sampling; high-speed link; Performance enhancement; Power consumption; Power demand; quantization; Quantization (signal); Receivers; Relativity; Reliability; Sampling; Spacetime

The scaling of analog-to-digital converter (ADC) power consumption with communication bandwidth imposes severe limits on its precision, which significantly impacts receiver performance. In this paper, we consider a "space-time" generalization of the flash architecture by allowing a fixed n...