Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 38; no. 5; pp. 888 - 897
• Main Authors: Lee, Sugil, Kim, Daewoo, Nguyen, Dong, Lee, Jongeun
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Accelerator architectures; Accelerators; Artificial neural networks; Computation; Computer simulation; Convolution; Convolutional neural network (CNN); Digital signal processing; digital signal processing (DSP) block; Field programmable gate arrays; field-programmable gate array (FPGA); Gate arrays; Hardware; Machine learning; multiply-and-accumulate (MAC); Neural networks; reduced precision; single-instruction multiple-data (SIMD); Table lookup; Throughput; Workload

Deep learning workloads, such as convolutional neural networks (CNNs) are important due to increasingly demanding high-performance hardware acceleration. One distinguishing feature of a deep learning workload is that it is inherently resilient to small numerical errors and thus works very well with...