An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 69; no. 9; pp. 3512 - 3525
• Main Authors: Maheshwari, Sachin, Serb, Alexander, Papavassiliou, Christos, Prodromakis, Themistoklis
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adiabatic; Adiabatic flow; Artificial neural networks; Capacitance; Capacitors; Comparators; Energy conservation; Energy consumption; energy-efficient; Memory devices; memristor; MOS devices; Neural networks; Neuromorphic computing; Power management; Random access memory; RLC circuits; RRAM; Switches; Synapses; Transistors
• DOI: 10.1109/TCSI.2022.3182577
• ISSN: 1549-8328

In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with 'memimpedace' elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at <inline-formula> <tex-math notation="LaTeX">100^{o}C </tex-math></inline-formula> across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance's quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).