A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

• Published in: IEEE journal of solid-state circuits Vol. 56; no. 9; pp. 2691 - 2700
• Main Authors: Chang, Dong-Jin, Choi, Michael, Ryu, Seung-Tak
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital conversion; Analog to digital converters; Analog-to-digital converter (ADC); Calibration; CMOS; Computer architecture; digital background calibration; Linearity; Noise levels; Power consumption; Prototypes; Redundancy; Sampling; sub-ranging architecture; Time-frequency analysis; time-interleaved (TI) ADC; Timing; timing-skew mismatch
• DOI: 10.1109/JSSC.2021.3073976
• ISSN: 0018-9200

This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from −40 to −63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step.