A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

• Published in: IEEE journal of solid-state circuits Vol. 54; no. 8; pp. 2243 - 2254
• Main Authors: Lee, Yuan-Sheng, Ho, Wei-Hsiang, Chen, Wei-Zen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth; Baud rate CDR; Bit error rate; Clocks; CMOS; Data recovery; demultiplexer; Detectors; Energy efficiency; integrating-type receiver; jitter tolerance (JTOL); optical receiver; Optical receivers; Oversampling; Power consumption; Sensitivity; Timing; Vibration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2019.2907804

This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 2 31 −1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about −13.8 and −8.7 dBm respectively, for a bit error rate (BER) of less than 10 −12 . The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm 2 . The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.