A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution - Liu, Leibo; Zhu, Wenping; Yin, Shouyi; Wei, Shaojun (IEEE transactions on computer-aided design of integrated circuits and systems, 2019)
Considering that the binary-feature-based approximate nearest neighbor (ANN) search technique has not been fully exploited to date, a multisegment binary feature-based hierarchical clustering tree model is proposed to achieve fast binary feature matching (FM). In addition, the multisegment vocabulary forest, is developed for the ease of hardware-oriented implementation. During the ANN searching process, the corresponding leaf nodes of each segment of the query feature are returned simultaneously to improve processing speed and accuracy. Furthermore, a hierarchical decomposition based on the term frequency-inverse document frequency is used to reduce the run-time search space and total memory footprint for object database storage. Finally, a fine-grained feature-level fully pipelined object recognition accelerator is implemented based on a dedicated design between FM and object scoring. The performance of the proposed object recognition accelerator is evaluated based on TSMC 65 nm CMOS technology. The accelerator achieves 22 M-vec/s and 6.8 \boldsymbol × 10^{8} vec/J in throughput and energy efficiency for full-HD resolution, respectively; these results represent a 10.6\boldsymbol × and 9\boldsymbol × improvement, respectively, relative to current state-of-the-art solutions. The average power consumption is 32.6 mW when operating at 200 MHz.