DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 11; pp. 2306 - 2319
• Main Authors: Peng, Xiaochen, Huang, Shanshi, Jiang, Hongwu, Lu, Anni, Yu, Shimeng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerators; Algorithms; Analog to digital conversion; Analog to digital converters; Artificial neural networks; Benchmark testing; Circuit design; Common Information Model (computing); Computer architecture; Computer memory; Deep learning; emerging nonvolatile memory (eNVM); Hardware; hardware accelerator; in-memory computing; Inference; Integrated circuit modeling; Machine learning; Microprocessors; on-chip training; System-on-chip; Training; Weight
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.3043731

DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from device-level, to circuit level and up to algorithm level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior inference version of DNN+NeuroSim framework available at https://github.com/neurosim/DNN_NeuroSim_V1.2 was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of an inference engine. In this work, we further investigated the impact of the "analog" emerging nonvolatile memory (eNVM)'s nonideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The latest training version of the DNN+NeuroSim framework is available at https://github.com/neurosim/DNN_NeuroSim_V2.1 .