Improved Neutral-Point Voltage Balancing Control With Time Delay Compensation and Antiwindup Loop for a Three-Level NPC Inverter

• Published in: IEEE transactions on industry applications Vol. 57; no. 5; pp. 4970 - 4980
• Main Authors: Lee, Hyun-Jun, Woo, Tae-gyeom, Kim, Sungmin, Yoon, Young-Doo
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Antiwindup loop; Balancing; Capacitors; carrier-based pulsewidth modulation (CBPWM); Compensation; Control stability; Control systems design; Controllers; Delay effects; Delays; digital delay; Electric potential; Inverters; Modulation; multilevel converter; neutral-point (NP) voltage balancing; Pulse duration; Pulse width modulation; Synthesis; three-level inverter; Time lag; Voltage; Voltage control; Windup

This article proposes an improved neutral-point voltage balancing control (NPVBC) with time delay compensation and an antiwindup loop based on a dynamic change limit for a three-level neutral-point clamped (NPC) voltage-source inverter. NPVBC is essential for a three-level NPC inverter since it has...