A Third-Order MAF Based QT1-PLL That is Robust Against Harmonically Distorted Grid Voltage With Frequency Deviation

• Published in: IEEE transactions on energy conversion Vol. 36; no. 3; pp. 1600 - 1613
• Main Authors: Mellouli, Mohamed, Hamouda, Mahmoud, Slama, Jaleleddine Ben Hadj, Al-Haddad, Kamal
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive algorithms; Delayed signal cancellation (DSC); Digital signal processing; Digital signal processors; distributed power generation; Dynamic response; Filtering algorithms; Frequency deviation; Frequency drift; Frequency estimation; Harmonic analysis; Harmonic distortion; Microprocessors; moving average filter (MAF); Phase locked loops; Phase locked systems; phase-locked loop (PLL); Power harmonic filters; power quality; Resonant frequencies; Robustness (mathematics); stability; Synchronism; Synchronization; Topology
• DOI: 10.1109/TEC.2021.3061027
• ISSN: 0885-8969

The quasi-type-l phase-locked loop (QT1-PLL) is a grid synchronization technique that has become very popular in recent years thanks to its attractive performance such as easy implementation, fast dynamic response, and good accuracy in steady-state operation. However, it is still vulnerable to operation under harmonically distorted grid voltages with frequency drift. This paper proposes a novel QT1-PLL based synchronization algorithm that makes an appropriate combination of two filters' types: an in-loop third-order moving average filter (MAF) with a reduced window width, and a simplified second-order fast delayed signal cancellation (FDSC) based prefiltering stage. The proposed PLL is named third-order MAF based QT1-PLL (TQT1-PLL). Though both TQT1-PLL's filters do not need any adaptive algorithm, it is able to reject non-triplen odd-harmonics and the fundamental frequency negative sequence (FFNS) even under grid frequency drift. Its correct operation is confirmed through numerical simulations and real-time implementation on a digital signal processor (DSP). Moreover, the obtained results confirm its ability to reduce the ripple in the estimated frequency and phase under distorted grid voltages and off-nominal frequency operation. Authors show also through an analytical development that the topology of the proposed TQT1-PLL can be extended to enable the rejection of the DC-offset.