Design-technology co-optimization for OxRRAM-based synaptic processing unit
In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit...
Saved in:
Published in | 2017 Symposium on VLSI Technology pp. T178 - T179 |
---|---|
Main Authors | , , , , , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
Published |
JSAP
01.06.2017
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification accuracy (94%) including device variability. To our knowledge, this is the first paper to discuss the tradeoff between single and multi-device synaptic weight in terms of design and technology using silicon data. We have demonstrated that high level of variability can be handled by the neuromorphic algorithm. The results presented in the paper has been obtained from 1Mb array. |
---|---|
AbstractList | In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement of a high number of distinct levels in synaptic weight has been established as a primary bottleneck for using a single NVM as a synaptic unit. We propose a mixed-radix encoding system for a multi-device synaptic unit achieving high classification accuracy (94%) including device variability. To our knowledge, this is the first paper to discuss the tradeoff between single and multi-device synaptic weight in terms of design and technology using silicon data. We have demonstrated that high level of variability can be handled by the neuromorphic algorithm. The results presented in the paper has been obtained from 1Mb array. |
Author | Schaafsma, S. Das, A. K. Raghavan, P. Kar, G. S. Fantini, A. Garbin, D. Furnemont, A. Mocuta, A. Rodopoulos, D. Stuijt, J. Degraeve, R. Donadio, G. Hody, H. Goux, L. Mallik, A. Debacker, P. |
Author_xml | – sequence: 1 givenname: A. surname: Mallik fullname: Mallik, A. email: Arindam.Mallik@imec.be – sequence: 2 givenname: D. surname: Garbin fullname: Garbin, D. – sequence: 3 givenname: A. surname: Fantini fullname: Fantini, A. – sequence: 4 givenname: D. surname: Rodopoulos fullname: Rodopoulos, D. – sequence: 5 givenname: R. surname: Degraeve fullname: Degraeve, R. – sequence: 6 givenname: J. surname: Stuijt fullname: Stuijt, J. – sequence: 7 givenname: A. K. surname: Das fullname: Das, A. K. – sequence: 8 givenname: S. surname: Schaafsma fullname: Schaafsma, S. – sequence: 9 givenname: P. surname: Debacker fullname: Debacker, P. – sequence: 10 givenname: G. surname: Donadio fullname: Donadio, G. – sequence: 11 givenname: H. surname: Hody fullname: Hody, H. – sequence: 12 givenname: L. surname: Goux fullname: Goux, L. – sequence: 13 givenname: G. S. surname: Kar fullname: Kar, G. S. – sequence: 14 givenname: A. surname: Furnemont fullname: Furnemont, A. – sequence: 15 givenname: A. surname: Mocuta fullname: Mocuta, A. – sequence: 16 givenname: P. surname: Raghavan fullname: Raghavan, P. |
BookMark | eNotj9tKwzAAhqMoOGefYDd9gdScD5djnoaVwZzejiRLa2BLSlPB-vQW3MXPd_PxwX8LrmKKHoAFRhWhGuv7z_p9vasIwrKSWissxAUotFRMCToNcXUJZgRzBbVQ5AYUOQeLGGFScCFn4PXB59BGOHj3FdMxtWPpEkzdEE7h1wwhxbJJfbn52W6Xb9Ca7A9lHqOZBFd2fXJ-Csa2_I5huAPXjTlmX5w5Bx9Pj7vVC6w3z-vVsoaOaDxAQwVV1jXUSWSQZcI5xA5cWEQtI9IJ1wgqGcFUIa8ayignjUeIG-axZJLOweK_G7z3-64PJ9OP-_N9-gePBFDA |
CitedBy_id | crossref_primary_10_1109_LED_2020_2986889 crossref_primary_10_1109_JIOT_2021_3058015 crossref_primary_10_1145_3524068 crossref_primary_10_1109_LES_2020_3025873 crossref_primary_10_1145_3462330 crossref_primary_10_1109_TED_2019_2894387 crossref_primary_10_7567_JJAP_57_06JA01 crossref_primary_10_1109_TPDS_2021_3065591 crossref_primary_10_1109_LED_2018_2872434 crossref_primary_10_3390_electronics11162592 crossref_primary_10_1109_TVLSI_2019_2951493 crossref_primary_10_1109_MDAT_2022_3148967 crossref_primary_10_1109_TED_2019_2961505 crossref_primary_10_1109_TNNLS_2021_3118451 crossref_primary_10_1145_3479156 |
ContentType | Conference Proceeding |
DBID | 6IE 6IH CBEJK RIE RIO |
DOI | 10.23919/VLSIT.2017.7998166 |
DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://proxy.k.utb.cz/login?url=https://ieeexplore.ieee.org/ sourceTypes: Publisher |
DeliveryMethod | fulltext_linktorsrc |
EISBN | 9784863486058 4863486057 |
EISSN | 2158-9682 |
EndPage | T179 |
ExternalDocumentID | 7998166 |
Genre | orig-research |
GroupedDBID | 6IE 6IH 6IL 6IN ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO IEGSK IJVOP OCL RIE RIL RIO |
ID | FETCH-LOGICAL-c291t-a3638bcf3c70a0b46cc04d56b03b427c6cf637421380e8f34352fe005a4e17473 |
IEDL.DBID | RIE |
IngestDate | Wed Jun 26 19:24:29 EDT 2024 |
IsPeerReviewed | false |
IsScholarly | true |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-LOGICAL-c291t-a3638bcf3c70a0b46cc04d56b03b427c6cf637421380e8f34352fe005a4e17473 |
ParticipantIDs | ieee_primary_7998166 |
PublicationCentury | 2000 |
PublicationDate | 2017-06 |
PublicationDateYYYYMMDD | 2017-06-01 |
PublicationDate_xml | – month: 06 year: 2017 text: 2017-06 |
PublicationDecade | 2010 |
PublicationTitle | 2017 Symposium on VLSI Technology |
PublicationTitleAbbrev | VLSIT |
PublicationYear | 2017 |
Publisher | JSAP |
Publisher_xml | – name: JSAP |
SSID | ssib042476567 ssib028086288 ssib030238738 |
Score | 2.3035636 |
Snippet | In this paper, we present a design-technology tradeoff analysis to implement a fully connected neural network using non-volatile OxRRAM cells. The requirement... |
SourceID | ieee |
SourceType | Publisher |
StartPage | T178 |
SubjectTerms | Arrays Classification algorithms Distortion Encoding Measurement Neuromorphics Software algorithms |
Title | Design-technology co-optimization for OxRRAM-based synaptic processing unit |
URI | https://ieeexplore.ieee.org/document/7998166 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV07T8MwELbaTkyAWsRbHhhxmtiunYwIqMojgEqLulWOYy-IpIJEAn495yRtATGwWJEVWdZd7Lvvct8dQidRoi1Y7YRI60I3wjKiwG2GIbSBtpayikgb34nRlF_PBrMWOl1xYYwxVfKZ8dxj9S8_zXXpQmV9CdggEKKN2qFPa67W8tuhofPN16W3XC-c8FtpMU65BNdF1oWHKIuCqP90-3g1cdld0mtW_tFipbIww00UL_dWJ5Y8e2WRePrzV9nG_25-C_XWXD78sLJS26hlsi66uagSN0ixCqxjnZMcro-XhpeJwZnF9-_j8VlMnKVL8dtHpuAFjRc1twBWwyVcCD00HV5OzkekaatANI2CgigGZw5UxLT0lZ9wobXP04EAoSWcSi20FQwQc8BC34SWgUNFrYHTqrgB_CLZDupkeWZ2EabKGguQiAsGMC8KHPixLJUyBWQzUHoPdZ0g5ou6csa8kcH-39MHaMMpo07EOkSd4rU0R2Dyi-S40vUX5GuomA |
link.rule.ids | 310,311,786,790,795,796,802,27958,55109 |
linkProvider | IEEE |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwjV3PT8IwFG4QD3pSA8bf9uDRjq0t7XY0KgFhaBAMN7J17cXIiG6J-tf7ug1Q48HLsixL0_Stfd_39r73ELoIYmXAa8dEGhu6EYaRCGAzXHzjKWMoK4S04VB0J_xu2p7W0OVKC6O1LpLPtGNvi3_5SapyGyprSeAGnhAbaBP8vBuUaq3l10N9i87XxbdsNxz_W3ExTrkE8CLL0kOUBV7Qeho89sY2v0s61dg_mqwUPqazg8Ll7MrUkmcnz2JHff4q3Pjf6e-i5lrNhx9WfmoP1fS8gfo3ReoGyVahdaxSksIB8lIpMzHAWXz_PhpdhcT6ugS_fcwjeEHhRakugNFwDkdCE006t-PrLqkaKxBFAy8jEYNdB0ZiSrqRG3OhlMuTtoBFizmVSigjGHBmj_mu9g0DSEWNhv0acQ0MRrJ9VJ-nc32AMI2MNkCKuGBA9ALP0h_DEikT4DbtSB2ihl2I2aKsnTGr1uDo78fnaKs7DgezQW_YP0bb1jBlWtYJqmevuT4FAJDFZ4XdvwD96avu |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2017+Symposium+on+VLSI+Technology&rft.atitle=Design-technology+co-optimization+for+OxRRAM-based+synaptic+processing+unit&rft.au=Mallik%2C+A.&rft.au=Garbin%2C+D.&rft.au=Fantini%2C+A.&rft.au=Rodopoulos%2C+D.&rft.date=2017-06-01&rft.pub=JSAP&rft.eissn=2158-9682&rft.spage=T178&rft.epage=T179&rft_id=info:doi/10.23919%2FVLSIT.2017.7998166&rft.externalDocID=7998166 |