A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface

• Published in: IEEE transactions on consumer electronics Vol. 65; no. 4; pp. 484 - 492
• Main Authors: Lee, Pil-Ho, Jang, Young-Chan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bridge circuits; byte synchronization; Calibration; Circuits; Clocks; CMOS; continuous time linear equalization; D-PHY; Delays; deserialization; Detectors; Electric potential; Equalization; Low speed; Metal oxides; Microprocessors; Mobile industry processor interface (MIPI); Phase detectors; Receivers; Semiconductors; Skew bridges; skew calibration; Synchronism; Synchronization; Time lag; Vibration; Voltage

A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronizati...