A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface

• Published in: IEEE transactions on consumer electronics Vol. 65; no. 4; pp. 484 - 492
• Main Authors: Lee, Pil-Ho, Jang, Young-Chan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bridge circuits; byte synchronization; Calibration; Circuits; Clocks; CMOS; continuous time linear equalization; D-PHY; Delays; deserialization; Detectors; Electric potential; Equalization; Low speed; Metal oxides; Microprocessors; Mobile industry processor interface (MIPI); Phase detectors; Receivers; Semiconductors; Skew bridges; skew calibration; Synchronism; Synchronization; Time lag; Vibration; Voltage
• DOI: 10.1109/TCE.2019.2942503
• ISSN: 0098-3063

A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronization and 1-to-8 deserialization for converting high-speed scalable low-voltage signals into low-speed low-voltage complementary metal-oxide semiconductor signals. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise owing to the use of the multiple bits supplied from the deserializer as a result of the phase detector for the skew calibration. It is performed via a four-step sequential process to use the minimum time delay. The proposed receiver bridge chip is implemented using a 0.11 μm CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the signal recovered using the proposed receiver is 50 ps at a data rate of 5.0 Gbps/lane on a printed circuit board FR-4 10 inch channel. The proposed skew calibration reduces the time skew among the four data lanes and one clock lane to less than 10 ps.