Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded Systems

• Published in: IEEE transactions on computers Vol. 70; no. 3; pp. 359 - 371
• Main Authors: Bazzaz, Mostafa, Hoseinghorban, Ali, Ejlali, Alireza
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Buffers; Embedded systems; Energy consumption; Energy harvesting; Hybrid systems; Memory management; non-volatile memories; Nonvolatile memory; Optimization; Optimization techniques; Power consumption; power management; Random access memory; Real time; Real-time embedded systems; Real-time systems; Software
• DOI: 10.1109/TC.2020.2988261
• ISSN: 0018-9340

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed correctly. In this article, we present a predictable fully non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. Since write buffers usually help with the performance problem but they make WCET estimation more complex, we also present a new low-overhead software-based optimization technique that makes the proposed system more predictable without imposing considerable overhead. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33 and 47 percent, respectively.