Design and implementation of a discontinuous SVM applied for a quasi Z-source inverter with power loss reduction
This study proposes a new control strategy for the quasi Z-source two-level three-phase inverter, accurate discontinuous SVM (AD-ZSVPWM). The proposed AD-ZSVPWM control technique enhances the output power quality by reducing total harmonic distortion (THD) and conduction losses. Low THD is achieved...
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Published in | JOURNAL OF POWER ELECTRONICS Vol. 24; no. 10; pp. 1584 - 1595 |
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Main Authors | , , , , , , |
Format | Journal Article |
Language | English |
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Springer Nature Singapore
01.10.2024
전력전자학회 |
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Abstract | This study proposes a new control strategy for the quasi Z-source two-level three-phase inverter, accurate discontinuous SVM (AD-ZSVPWM). The proposed AD-ZSVPWM control technique enhances the output power quality by reducing total harmonic distortion (THD) and conduction losses. Low THD is achieved by increasing the algorithm’s accuracy using a division of six vector states in each switching period and the distribution of six shoot-through states within the period. The conduction losses are reduced by splitting each sector into two subsectors of 30°. The proposed control scheme has the following advantages: reduced THD, low conduction loss, and increased boosting factor. MATLAB/Simulink software is used, and an experimental test is conducted to validate the proposed strategy. PLECS software is utilized to calculate the switching and conduction losses. For experimental verification, a hardware test bench comprising a dSPACE DS1104 board that controls a three-phase quasi Z-source inverter that supplies an R-L load is used. Simulation and hardware results show that the proposed scheme provides improved performance in terms of power quality and power loss reduction. |
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AbstractList | This study proposes a new control strategy for the quasi Z-source two-level three-phase inverter, accurate discontinuous SVM (AD-ZSVPWM). The proposed AD-ZSVPWM control technique enhances the output power quality by reducing total harmonic distortion (THD) and conduction losses. Low THD is achieved by increasing the algorithm’s accuracy using a division of six vector states in each switching period and the distribution of six shoot-through states within the period. The conduction losses are reduced by splitting each sector into two subsectors of 30°. The proposed control scheme has the following advantages: reduced THD, low conduction loss, and increased boosting factor. MATLAB/Simulink software is used, and an experimental test is conducted to validate the proposed strategy. PLECS software is utilized to calculate the switching and conduction losses. For experimental verification, a hardware test bench comprising a dSPACE DS1104 board that controls a three-phase quasi Z-source inverter that supplies an R-L load is used. Simulation and hardware results show that the proposed scheme provides improved performance in terms of power quality and power loss reduction. KCI Citation Count: 0 This study proposes a new control strategy for the quasi Z-source two-level three-phase inverter, accurate discontinuous SVM (AD-ZSVPWM). The proposed AD-ZSVPWM control technique enhances the output power quality by reducing total harmonic distortion (THD) and conduction losses. Low THD is achieved by increasing the algorithm’s accuracy using a division of six vector states in each switching period and the distribution of six shoot-through states within the period. The conduction losses are reduced by splitting each sector into two subsectors of 30°. The proposed control scheme has the following advantages: reduced THD, low conduction loss, and increased boosting factor. MATLAB/Simulink software is used, and an experimental test is conducted to validate the proposed strategy. PLECS software is utilized to calculate the switching and conduction losses. For experimental verification, a hardware test bench comprising a dSPACE DS1104 board that controls a three-phase quasi Z-source inverter that supplies an R-L load is used. Simulation and hardware results show that the proposed scheme provides improved performance in terms of power quality and power loss reduction. |
Author | Stojcevski, Alex Mekhilef, Saad Sabeur, Nassereddine Kermadi, Mostefa Berkouk, El Madjid Chaib, Ibtissam Seyedmahmoudian, Mehdi |
Author_xml | – sequence: 1 givenname: Ibtissam orcidid: 0000-0002-5899-8745 surname: Chaib fullname: Chaib, Ibtissam email: ibtissam.chaib@g.enp.edu.dz organization: Laboratoire de Commande de Processus (LCP), École Nationale Polytechnique Algiers, University Kasdi Merbah Ouargla – sequence: 2 givenname: Mostefa surname: Kermadi fullname: Kermadi, Mostefa organization: Power Electronics and Renewable Energy Research Laboratory (PEARL), Universiti Malaya – sequence: 3 givenname: Saad surname: Mekhilef fullname: Mekhilef, Saad organization: School of Science, Computing and Engineering Technologies, Swinburne University of Technology – sequence: 4 givenname: El Madjid surname: Berkouk fullname: Berkouk, El Madjid organization: Laboratoire de Commande de Processus (LCP), École Nationale Polytechnique Algiers – sequence: 5 givenname: Nassereddine surname: Sabeur fullname: Sabeur, Nassereddine organization: Power Electronics and Renewable Energy Research Laboratory (PEARL), Universiti Malaya – sequence: 6 givenname: Mehdi surname: Seyedmahmoudian fullname: Seyedmahmoudian, Mehdi organization: School of Science, Computing and Engineering Technologies, Swinburne University of Technology – sequence: 7 givenname: Alex surname: Stojcevski fullname: Stojcevski, Alex organization: School of Science, Computing and Engineering Technologies, Swinburne University of Technology |
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Cites_doi | 10.1109/TIA.2006.872927 10.1080/09398368.2011.11463792 10.1109/TPEL.2020.3009866 10.1007/s43236-022-00536-5 10.1109/JESTPE.2017.2763974 10.1109/TIE.2022.3212423 10.1109/TIE.2021.3139185 10.1016/j.ijepes.2018.07.034 10.1016/j.ijepes.2012.10.008 10.1109/TIE.2018.2798611 10.1109/JESTPE.2020.3002684 10.1049/iet-pel.2013.0903 10.1109/TEC.2006.874232 10.1109/TIE.2022.3183276 10.1002/cta.2395 10.1109/TIA.2003.808920 10.1109/TPEL.2013.2269539 10.1109/TPEL.2005.850927 10.3390/electronics11142164 10.1109/TPEL.2010.2089806 10.1109/APEC.2018.8341577 10.1109/EPQU.2011.6128914 10.53316/sepoc2021.034 10.1109/IECON43393.2020.9255384 |
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Title | Design and implementation of a discontinuous SVM applied for a quasi Z-source inverter with power loss reduction |
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