Compaction of test response at self-testing in the programmable logic matrices

Consideration was given to a controllable architecture enabling easy, simple and prompt self-testing in the programmable logic matrix. An approach was proposed to reduce the amount of self-testing hardware by compacting the test response by mod 2 convolution schemes through reconfiguration of the su...

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Published inAutomation and remote control Vol. 74; no. 2; pp. 264 - 274
Main Author Aksenova, G. P.
Format Journal Article
LanguageEnglish
Published Dordrecht SP MAIK Nauka/Interperiodica 01.02.2013
Subjects
CAE) and Design
Calculus of Variations and Optimal Control; Optimization
Compacting
Computer-Aided Engineering (CAD
Control
Hardware
Joints
Logic
Mathematics
Mathematics and Statistics
Mechanical Engineering
Mechatronics
Reconfiguration
Reliability
Remote control
Robotics
Safety
Stability
Systems Theory
Technical Diagnostics
Viability
Compaction
External Input
Remote Control
Output Response
Test Pattern
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Abstract Consideration was given to a controllable architecture enabling easy, simple and prompt self-testing in the programmable logic matrix. An approach was proposed to reduce the amount of self-testing hardware by compacting the test response by mod 2 convolution schemes through reconfiguration of the subject of diagnosis programmed in the matrix and using its standard connections.
AbstractList Consideration was given to a controllable architecture enabling easy, simple and prompt self-testing in the programmable logic matrix. An approach was proposed to reduce the amount of self-testing hardware by compacting the test response by mod 2 convolution schemes through reconfiguration of the subject of diagnosis programmed in the matrix and using its standard connections.
Author Aksenova, G. P.
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Cites_doi 10.1109/TCAD.2010.2041852
10.1109/TCAD.2004.823341
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10.1134/S000511791012012X
10.1109/TCAD.2010.2051096
10.1134/S0005117907010146
10.1109/TCAD.2011.2176733
10.1049/iet-cdt:20080051
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Keywords Compaction
External Input
Remote Control
Output Response
Test Pattern
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References LeeL.-J.TsengW.-D.LinR.-B.ChangC.-H.2n-pattern Run-length for Test Data CompressionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201231464464810.1109/TCAD.2011.2176733
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LeeK.-J.LienW.-C.HsiehT.-Y.Test Response Compaction via Output Bit SelectionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.2011301016341544
AksenovaG.P.Control-ready Architecture for Self-Testing in Programmable Logical Matrix StructuresAutom. Remote Control2010711226332643279108810.1134/S000511791012012X
LeeD.RoyK.Viterbi-based Efficient Test Data CompressionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201231461061910.1109/TCAD.2011.2172609
Li, L., Chakrabarty, K., Kajihara, S., and Swaminathan, S., Three-stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs, IEE Proc., online no. 20045150.
SinanogluO.All-MullaM.TahaM.Utilization of Inverse Compatibility for Test Cost ReductionIET Comput. Digit. Tech.20093219520410.1049/iet-cdt:20080051
TenentesV.KavousianosX.KalligerosE.Single and Variable-state-skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP CoresIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201029101640164410.1109/TCAD.2010.2051096
MitraS.KimK.S.X-compact: An Efficient Response Compaction TechniqueIEEE Trans. Comput. Aided Design Integr. Circ. Syst.200423342143210.1109/TCAD.2004.823341
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G.P. Aksenova (9827_CR10) 2007; 68
9827_CR1
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V. Tenentes (9827_CR5) 2010; 29
O. Sinanoglu (9827_CR4) 2009; 3
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G.P. Aksenova (9827_CR9) 2010; 71
N. Mukherjee (9827_CR3) 2010; 29
S. Mitra (9827_CR6) 2004; 23
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– reference: TenentesV.KavousianosX.KalligerosE.Single and Variable-state-skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP CoresIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201029101640164410.1109/TCAD.2010.2051096
– reference: MitraS.KimK.S.X-compact: An Efficient Response Compaction TechniqueIEEE Trans. Comput. Aided Design Integr. Circ. Syst.200423342143210.1109/TCAD.2004.823341
– reference: AksenovaG.P.Control-ready Architecture for Self-Testing in Programmable Logical Matrix StructuresAutom. Remote Control2010711226332643279108810.1134/S000511791012012X
– reference: LeeD.RoyK.Viterbi-based Efficient Test Data CompressionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201231461061910.1109/TCAD.2011.2172609
– reference: Li, L., Chakrabarty, K., Kajihara, S., and Swaminathan, S., Three-stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs, IEE Proc., online no. 20045150.
– reference: SinanogluO.All-MullaM.TahaM.Utilization of Inverse Compatibility for Test Cost ReductionIET Comput. Digit. Tech.20093219520410.1049/iet-cdt:20080051
– reference: LeeK.-J.LienW.-C.HsiehT.-Y.Test Response Compaction via Output Bit SelectionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.2011301016341544
– reference: LeeL.-J.TsengW.-D.LinR.-B.ChangC.-H.2n-pattern Run-length for Test Data CompressionIEEE Trans. Comput. Aided Design Integr. Circ. Syst.201231464464810.1109/TCAD.2011.2176733
– reference: AksenovaG.P.KhalchevV.F.The Method of Parallel-Sequential Built-in Self-testing in Integrated Circuits of the type SFPGASAutom. Remote Control20076811491591195.9409810.1134/S0005117907010146
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  publication-title: IET Comput. Digit. Tech.
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SubjectTerms CAE) and Design
Calculus of Variations and Optimal Control; Optimization
Compacting
Computer-Aided Engineering (CAD
Control
Hardware
Joints
Logic
Mathematics
Mathematics and Statistics
Mechanical Engineering
Mechatronics
Reconfiguration
Reliability
Remote control
Robotics
Safety
Stability
Systems Theory
Technical Diagnostics
Viability
Title Compaction of test response at self-testing in the programmable logic matrices
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